This Repository contains the verification of a Synchronous FIFO design using SystemVerilog and SystemVerilogAssertions

[DAC 2026] QiMeng-CodeV-SVA: Training Specialized LLMs for Hardware Assertion Generation via RTL-Grounded Bidirectional Data Synthesis

✅ Formal verification of a 16-bit SIMD processor

A simple tool that converts hardware specification text into SystemVerilog Assertions using an LLM.

RV32I RISC-V core written in SystemVerilog, with an emphasis on coverage-driven verification using constrained-random stimulus, SVA assertions, and functional coverage

Parameterized serial router with cycle-compatible SystemVerilog RTL, reusable UVM 1.2 verification, assertions, coverage closure, differential testing, and mutation analysis.

A synthesizable UART design with an AMBA APB3 slave interface. Verified using SystemVerilog, Assertions (SVA), and functional coverage.

Floating point multiplier with rounder, exception handler and assertions in SystemVerilog. Project is part of class HW-2, ECE AUTH.

Формальная и функциональная верификация переходника с интерфейса valid-ready на интерфейс valid-credit.

Parameterized dual-clock asynchronous FIFO designed in Verilog for safe Clock Domain Crossing (CDC). Implements Gray-code pointer encoding, 2-flip-flop synchronizers, and conservative full/empty flag logic following Cummings SNUG 2002 architecture. Verified with a 600-line self-checking reference testbench and SVA protocol assertions across 7 test.

Parameterized asynchronous FIFO in SystemVerilog with Gray-code pointers, 2-flop CDC synchronizers, and a self-checking SVA/coverage-driven testbench.