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1. rv32i-pipelined-cpu rv32i-pipelined-cpu Public

   5-Stage Hazard-Aware Pipelined RISC-V CPU Core (RV32I-Lite) in Verilog, featuring data forwarding, load-use stalling, branch flushes, and Yosys synthesis verification.

   Verilog 1

2. Adaptive-Audio-DSP-Restoration-Noise-Cancellation-Pipeline Adaptive-Audio-DSP-Restoration-Noise-Cancellation-Pipeline Public

   Python

3. cdc-async-fifo cdc-async-fifo Public

   Parameterized dual-clock asynchronous FIFO designed in Verilog for safe Clock Domain Crossing (CDC). Implements Gray-code pointer encoding, 2-flip-flop synchronizers, and conservative full/empty fl…

   Verilog

4. rv32i-coverage-closure rv32i-coverage-closure Public

   Automated machine-learning verification framework using cocotb, cocotb-coverage, and UCB1 Multi-Armed Bandit algorithm to accelerate functional coverage closure on a 5-stage pipelined RV32I CPU. C…

   Verilog