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8385815: [CRaC] Fix aarch64 failing testcases #321

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104cdff
8385815: CRaC: Fix aarch64 failing testcases
jankratochvil Jun 2, 2026
6c349cd
Unify glibc features numbering
jankratochvil Jun 8, 2026
dd9a56c
Compilation fixes
jankratochvil Jun 8, 2026
2d75c5d
aarch64 compilation fixes
jankratochvil Jun 8, 2026
3fee099
Fix x86 testcases
jankratochvil Jun 8, 2026
e485a96
Fix whitespace
jankratochvil Jun 8, 2026
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2 changes: 1 addition & 1 deletion src/hotspot/cpu/aarch64/vmStructs_aarch64.hpp
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Expand Up @@ -41,7 +41,7 @@

#define VM_LONG_CONSTANTS_CPU(declare_constant, declare_preprocessor_constant)

#define DECLARE_INT_CPU_FEATURE_CONSTANT(id, name) GENERATE_VM_INT_CONSTANT_ENTRY(VM_Version::CPU_##id)
#define DECLARE_INT_CPU_FEATURE_CONSTANT(id, name, bit) GENERATE_VM_INT_CONSTANT_ENTRY(VM_Version::CPU_##id)
#define VM_INT_CPU_FEATURE_CONSTANTS CPU_FEATURE_FLAGS(DECLARE_INT_CPU_FEATURE_CONSTANT)

#endif // CPU_AARCH64_VMSTRUCTS_AARCH64_HPP
18 changes: 4 additions & 14 deletions src/hotspot/cpu/aarch64/vm_version_aarch64.cpp
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Expand Up @@ -59,8 +59,6 @@
GLIBC_UNSUPPORTED(SVEBITPERM); \
GLIBC_UNSUPPORTED(SVE2 ); \
GLIBC_UNSUPPORTED(A53MAC ); \
GLIBC_UNSUPPORTED(ECV ); \
GLIBC_UNSUPPORTED(WFXT ); \
GLIBC_UNSUPPORTED(NOTPACA ); \
/**/
#include "runtime/abstract_vm_version.inline.hpp"
Expand Down Expand Up @@ -89,7 +87,7 @@ bool VM_Version::_ic_ivau_trapped;
VM_Version::VM_Features VM_Version::_features;
VM_Version::VM_Features VM_Version::_cpu_features;

#define DECLARE_CPU_FEATURE_NAME(id, name) XSTR(name),
#define DECLARE_CPU_FEATURE_NAME(id, name, bit) XSTR(name),
const char* VM_Version::_features_names[] = { CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_NAME)};
#undef DECLARE_CPU_FEATURE_NAME

Expand Down Expand Up @@ -888,17 +886,9 @@ bool VM_Version::cpu_features_binary(VM_Version::VM_Features *data) {
}

VM_Features VM_Version::CPUFeatures_generic() {
VM_Features retval;
retval.set_feature(CPU_FP);
retval.set_feature(CPU_ASIMD);
// PACA cannot be made compatible between CPUs that do and do not support it.
if (_cpu_features.supports_feature(CPU_PACA)) {
retval.set_feature(CPU_PACA);
}
if (_cpu_features.supports_feature(CPU_NOTPACA)) {
retval.set_feature(CPU_NOTPACA);
}
return retval;
// CPU_PACA and non-PACA processors cannot share the same image. Also we cannot disable glibc using features like CPU_LSE.
vm_exit_during_initialization("-XX:CPUFeatures=generic is not available on aarch64");
ShouldNotReachHere();
}

void VM_Version::print_using_features_cr() {
Expand Down
56 changes: 29 additions & 27 deletions src/hotspot/cpu/aarch64/vm_version_aarch64.hpp
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Expand Up @@ -34,37 +34,39 @@

class VM_Feature_Flag {
public:
#define CPU_FEATURE_FLAGS(decl) \
decl(FP, fp ) \
decl(ASIMD, asimd ) \
decl(EVTSTRM, evtstrm ) \
decl(AES, aes ) \
decl(PMULL, pmull ) \
decl(SHA1, sha1 ) \
decl(SHA2, sha256 ) \
decl(CRC32, crc32 ) \
decl(LSE, lse ) \
decl(FPHP, fphp ) \
decl(ASIMDHP, asimdhp ) \
decl(DCPOP, dcpop ) \
decl(SHA3, sha3 ) \
decl(SHA512, sha512 ) \
decl(SVE, sve ) \
decl(SB, sb ) \
decl(PACA, paca ) \
decl(SVEBITPERM, svebitperm) \
decl(SVE2, sve2 ) \
decl(A53MAC, a53mac ) \
decl(ECV, ecv ) \
decl(WFXT, wfxt ) \
decl(NOTPACA, notpaca ) \
#define CPU_FEATURE_FLAGS(decl) \
decl(FP, fp, 0) \
decl(ASIMD, asimd, 1) \
decl(EVTSTRM, evtstrm, 2) \
decl(AES, aes, 3) \
decl(PMULL, pmull, 4) \
decl(SHA1, sha1, 5) \
decl(SHA2, sha256, 6) \
decl(CRC32, crc32, 7) \
decl(LSE, lse, 8) \
decl(FPHP, fphp, 9) \
decl(ASIMDHP, asimdhp, 10) \
decl(DCPOP, dcpop, 11) \
decl(SHA3, sha3, 12) \
decl(SHA512, sha512, 13) \
decl(SVE, sve, 14) \
decl(SB, sb, 15) \
decl(PACA, paca, 16) \
decl(SVEBITPERM, svebitperm, 17) \
decl(SVE2, sve2, 18) \
decl(A53MAC, a53mac, 19) \
decl(ECV, ecv, 20) \
decl(WFXT, wfxt, 21) \
/* These features are added for CRaC. */ \
decl(NOTPACA, notpaca, 63) \
/**/

enum Feature_Flag {
#define DECLARE_CPU_FEATURE_FLAG(id, name) CPU_##id,
#define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (bit),
CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG)
#undef DECLARE_CPU_FEATURE_FLAG
MAX_CPU_FEATURES
MAX_CPU_FEATURES,
FIRST_GLIBC_FEATURE = CPU_NOTPACA
};
};

Expand Down Expand Up @@ -215,7 +217,7 @@ class VM_Version : public Abstract_VM_Version, public VM_Feature_Flag {
static const char* _features_names[];

// Feature identification
#define CPU_FEATURE_DETECTION(id, name) \
#define CPU_FEATURE_DETECTION(id, name, bit) \
static bool supports_##name() { return supports_feature(CPU_##id); }
CPU_FEATURE_FLAGS(CPU_FEATURE_DETECTION)
#undef CPU_FEATURE_DETECTION
Expand Down
2 changes: 1 addition & 1 deletion src/hotspot/cpu/x86/vmStructs_x86.hpp
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Expand Up @@ -46,7 +46,7 @@

#define VM_LONG_CONSTANTS_CPU(declare_constant, declare_preprocessor_constant)

#define DECLARE_LONG_CPU_FEATURE_CONSTANT(id, name) GENERATE_VM_LONG_CONSTANT_ENTRY(VM_Version::CPU_##id)
#define DECLARE_LONG_CPU_FEATURE_CONSTANT(id, name, bit) GENERATE_VM_LONG_CONSTANT_ENTRY(VM_Version::CPU_##id)
#define VM_LONG_CPU_FEATURE_CONSTANTS CPU_FEATURE_FLAGS(DECLARE_LONG_CPU_FEATURE_CONSTANT)

#endif // CPU_X86_VMSTRUCTS_X86_HPP
2 changes: 1 addition & 1 deletion src/hotspot/cpu/x86/vm_version_x86.cpp
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Expand Up @@ -144,7 +144,7 @@ int VM_Version::_stepping;
bool VM_Version::_has_intel_jcc_erratum;
VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };

#define DECLARE_CPU_FEATURE_NAME(id, name) XSTR(name),
#define DECLARE_CPU_FEATURE_NAME(id, name, bit) name,
const char* VM_Version::_features_names[] = { CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_NAME)};
#undef DECLARE_CPU_FEATURE_NAME

Expand Down
185 changes: 94 additions & 91 deletions src/hotspot/cpu/x86/vm_version_x86.hpp
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Expand Up @@ -40,101 +40,104 @@ class VM_Feature_Flag {
public:
enum Feature_Flag {
#define CPU_FEATURE_FLAGS(decl) \
decl(CX8, cx8 ) /* next bits are from cpuid 1 (EDX) */ \
decl(CMOV, cmov ) \
decl(FXSR, fxsr ) \
decl(HT, ht ) \
\
decl(MMX, mmx ) \
decl(3DNOW_PREFETCH, 3dnowpref ) /* Processor supports 3dnow prefetch and prefetchw instructions */ \
/* may not necessarily support other 3dnow instructions */ \
decl(SSE, sse ) \
decl(SSE2, sse2 ) \
\
decl(SSE3, sse3 ) /* SSE3 comes from cpuid 1 (ECX) */ \
decl(SSSE3, ssse3 ) \
decl(SSE4A, sse4a ) \
decl(SSE4_1, sse4.1 ) \
\
decl(SSE4_2, sse4.2 ) \
decl(POPCNT, popcnt ) \
decl(LZCNT, lzcnt ) \
decl(TSC, tsc ) \
\
decl(TSCINV_BIT, tscinvbit ) \
decl(TSCINV, tscinv ) \
decl(AVX, avx ) \
decl(AVX2, avx2 ) \
\
decl(AES, aes ) \
decl(ERMS, erms ) /* enhanced 'rep movsb/stosb' instructions */ \
decl(CLMUL, clmul ) /* carryless multiply for CRC */ \
decl(BMI1, bmi1 ) \
\
decl(BMI2, bmi2 ) \
decl(RTM, rtm ) /* Restricted Transactional Memory instructions */ \
decl(ADX, adx ) \
decl(AVX512F, avx512f ) /* AVX 512bit foundation instructions */ \
\
decl(AVX512DQ, avx512dq ) \
decl(AVX512PF, avx512pf ) \
decl(AVX512ER, avx512er ) \
decl(AVX512CD, avx512cd ) \
\
decl(AVX512BW, avx512bw ) /* Byte and word vector instructions */ \
decl(AVX512VL, avx512vl ) /* EVEX instructions with smaller vector length */ \
decl(SHA, sha ) /* SHA instructions */ \
decl(FMA, fma ) /* FMA instructions */ \
\
decl(VZEROUPPER, vzeroupper ) /* Vzeroupper instruction */ \
decl(AVX512_VPOPCNTDQ, avx512_vpopcntdq ) /* Vector popcount */ \
decl(AVX512_VPCLMULQDQ, avx512_vpclmulqdq) /* Vector carryless multiplication */ \
decl(AVX512_VAES, avx512_vaes ) /* Vector AES instruction */ \
\
decl(AVX512_VNNI, avx512_vnni ) /* Vector Neural Network Instructions */ \
decl(FLUSH, clflush ) /* flush instruction */ \
decl(FLUSHOPT, clflushopt ) /* flusopth instruction */ \
decl(CLWB, clwb ) /* clwb instruction */ \
\
decl(AVX512_VBMI2, avx512_vbmi2 ) /* VBMI2 shift left double instructions */ \
decl(AVX512_VBMI, avx512_vbmi ) /* Vector BMI instructions */ \
decl(HV, hv ) /* Hypervisor instructions */ \
decl(SERIALIZE, serialize ) /* CPU SERIALIZE */ \
decl(RDTSCP, rdtscp ) /* RDTSCP instruction */ \
decl(RDPID, rdpid ) /* RDPID instruction */ \
decl(FSRM, fsrm ) /* Fast Short REP MOV */ \
decl(GFNI, gfni ) /* Vector GFNI instructions */ \
decl(AVX512_BITALG, avx512_bitalg ) /* Vector sub-word popcount and bit gather instructions */\
decl(F16C, f16c ) /* Half-precision and single precision FP conversion instructions*/ \
decl(PKU, pku ) /* Protection keys for user-mode pages */ \
decl(OSPKE, ospke ) /* OS enables protection keys */ \
decl(CET_IBT, cet_ibt ) /* Control Flow Enforcement - Indirect Branch Tracking */ \
decl(CET_SS, cet_ss ) /* Control Flow Enforcement - Shadow Stack */ \
decl(AVX512_IFMA, avx512_ifma ) /* Integer Vector FMA instructions*/ \
decl(AVX_IFMA, avx_ifma ) /* 256-bit VEX-coded variant of AVX512-IFMA*/ \
decl(APX_F, apx_f ) /* Intel Advanced Performance Extensions*/ \
decl(SHA512, sha512 ) /* SHA512 instructions*/ \
decl(AVX512_FP16, avx512_fp16 ) /* AVX512 FP16 ISA support*/ \
decl(AVX10_1, avx10_1 ) /* AVX10 512 bit vector ISA Version 1 support*/ \
decl(AVX10_2, avx10_2 ) /* AVX10 512 bit vector ISA Version 2 support*/ \
decl(HYBRID, hybrid ) /* Hybrid architecture */ \
decl(FMA4, fma4 ) \
decl(MOVBE, movbe ) \
decl(OSXSAVE, osxsave ) \
decl(IBT, ibt ) \
decl(SHSTK, shstk ) /* Also known as cet_ss */ \
decl(XSAVE, xsave ) \
decl(CMPXCHG16, cmpxchg16 ) /* Also known in cpuinfo as cx16 and in glibc as cmpxchg16b */ \
decl(LAHFSAHF, lahfsahf ) /* Also known in cpuinfo as lahf_lm and in glibc as lahf64_sahf64 */ \
decl(HTT, htt ) /* hotspot calls it 'ht' but that is affected by threads_per_core() */ \
decl(XSAVEC, xsavec ) \
decl(AVX_Fast_Unaligned_Load, avx_fast_unaligned_load) \
decl(CX8, "cx8", 0) /* next bits are from cpuid 1 (EDX) */ \
decl(CMOV, "cmov", 1) \
decl(FXSR, "fxsr", 2) \
decl(HT, "ht", 3) \
\
decl(MMX, "mmx", 4) \
decl(3DNOW_PREFETCH, "3dnowpref", 5) /* Processor supports 3dnow prefetch and prefetchw instructions */ \
/* may not necessarily support other 3dnow instructions */ \
decl(SSE, "sse", 6) \
decl(SSE2, "sse2", 7) \
\
decl(SSE3, "sse3", 8 ) /* SSE3 comes from cpuid 1 (ECX) */ \
decl(SSSE3, "ssse3", 9 ) \
decl(SSE4A, "sse4a", 10) \
decl(SSE4_1, "sse4.1", 11) \
\
decl(SSE4_2, "sse4.2", 12) \
decl(POPCNT, "popcnt", 13) \
decl(LZCNT, "lzcnt", 14) \
decl(TSC, "tsc", 15) \
\
decl(TSCINV_BIT, "tscinvbit", 16) \
decl(TSCINV, "tscinv", 17) \
decl(AVX, "avx", 18) \
decl(AVX2, "avx2", 19) \
\
decl(AES, "aes", 20) \
decl(ERMS, "erms", 21) /* enhanced 'rep movsb/stosb' instructions */ \
decl(CLMUL, "clmul", 22) /* carryless multiply for CRC */ \
decl(BMI1, "bmi1", 23) \
\
decl(BMI2, "bmi2", 24) \
decl(RTM, "rtm", 25) /* Restricted Transactional Memory instructions */ \
decl(ADX, "adx", 26) \
decl(AVX512F, "avx512f", 27) /* AVX 512bit foundation instructions */ \
\
decl(AVX512DQ, "avx512dq", 28) \
decl(AVX512PF, "avx512pf", 29) \
decl(AVX512ER, "avx512er", 30) \
decl(AVX512CD, "avx512cd", 31) \
\
decl(AVX512BW, "avx512bw", 32) /* Byte and word vector instructions */ \
decl(AVX512VL, "avx512vl", 33) /* EVEX instructions with smaller vector length */ \
decl(SHA, "sha", 34) /* SHA instructions */ \
decl(FMA, "fma", 35) /* FMA instructions */ \
\
decl(VZEROUPPER, "vzeroupper", 36) /* Vzeroupper instruction */ \
decl(AVX512_VPOPCNTDQ, "avx512_vpopcntdq", 37) /* Vector popcount */ \
decl(AVX512_VPCLMULQDQ, "avx512_vpclmulqdq", 38) /* Vector carryless multiplication */ \
decl(AVX512_VAES, "avx512_vaes", 39) /* Vector AES instruction */ \
\
decl(AVX512_VNNI, "avx512_vnni", 40) /* Vector Neural Network Instructions */ \
decl(FLUSH, "clflush", 41) /* flush instruction */ \
decl(FLUSHOPT, "clflushopt", 42) /* flusopth instruction */ \
decl(CLWB, "clwb", 43) /* clwb instruction */ \
\
decl(AVX512_VBMI2, "avx512_vbmi2", 44) /* VBMI2 shift left double instructions */ \
decl(AVX512_VBMI, "avx512_vbmi", 45) /* Vector BMI instructions */ \
decl(HV, "hv", 46) /* Hypervisor instructions */ \
decl(SERIALIZE, "serialize", 47) /* CPU SERIALIZE */ \
decl(RDTSCP, "rdtscp", 48) /* RDTSCP instruction */ \
decl(RDPID, "rdpid", 49) /* RDPID instruction */ \
decl(FSRM, "fsrm", 50) /* Fast Short REP MOV */ \
decl(GFNI, "gfni", 51) /* Vector GFNI instructions */ \
decl(AVX512_BITALG, "avx512_bitalg", 52) /* Vector sub-word popcount and bit gather instructions */\
decl(F16C, "f16c", 53) /* Half-precision and single precision FP conversion instructions*/ \
decl(PKU, "pku", 54) /* Protection keys for user-mode pages */ \
decl(OSPKE, "ospke", 55) /* OS enables protection keys */ \
decl(CET_IBT, "cet_ibt", 56) /* Control Flow Enforcement - Indirect Branch Tracking */ \
decl(CET_SS, "cet_ss", 57) /* Control Flow Enforcement - Shadow Stack */ \
decl(AVX512_IFMA, "avx512_ifma", 58) /* Integer Vector FMA instructions*/ \
decl(AVX_IFMA, "avx_ifma", 59) /* 256-bit VEX-coded variant of AVX512-IFMA*/ \
decl(APX_F, "apx_f", 60) /* Intel Advanced Performance Extensions*/ \
decl(SHA512, "sha512", 61) /* SHA512 instructions*/ \
decl(AVX512_FP16, "avx512_fp16", 62) /* AVX512 FP16 ISA support*/ \
decl(AVX10_1, "avx10_1", 63) /* AVX10 512 bit vector ISA Version 1 support*/ \
decl(AVX10_2, "avx10_2", 64) /* AVX10 512 bit vector ISA Version 2 support*/ \
decl(HYBRID, "hybrid", 65) /* Hybrid architecture */ \
/* These features are added for CRaC for GLIBC_TUNABLES=glibc.cpu.hwcaps . */ \
decl(FMA4, "fma4", 117) \
decl(MOVBE, "movbe", 118) \
decl(OSXSAVE, "osxsave", 119) \
decl(IBT, "ibt", 120) \
decl(SHSTK, "shstk", 121) /* Also known as cet_ss */ \
decl(XSAVE, "xsave", 122) \
decl(CMPXCHG16, "cmpxchg16", 123) /* Also known in cpuinfo as cx16 and in glibc as cmpxchg16b */ \
decl(LAHFSAHF, "lahfsahf", 124) /* Also known in cpuinfo as lahf_lm and in glibc as lahf64_sahf64 */ \
decl(HTT, "htt", 125) /* hotspot calls it 'ht' but that is affected by threads_per_core() */ \
decl(XSAVEC, "xsavec", 126) \
decl(AVX_Fast_Unaligned_Load, "avx_fast_unaligned_load", 127) \
/**/

#define DECLARE_CPU_FEATURE_FLAG(id, name) CPU_##id,
#define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (bit),

@TimPushkin TimPushkin Jun 9, 2026

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Would it be possible to have two versions: with and without an explicit ID to minimize the difference with the mainline? Currently CPU-features is already the most frequently conflicting part when merging with the mainline...

CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG)
#undef DECLARE_CPU_FEATURE_FLAG
MAX_CPU_FEATURES
MAX_CPU_FEATURES,
// Define a window of unused features so that adding new CPU_* upstream does not shift the GLIBC features.
FIRST_GLIBC_FEATURE = CPU_FMA4
};
};

Expand Down
4 changes: 2 additions & 2 deletions src/hotspot/share/jvmci/vmStructs_jvmci.cpp
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Expand Up @@ -1017,7 +1017,7 @@
static_field(VM_Version, _rop_protection, bool) \
volatile_nonstatic_field(JavaFrameAnchor, _last_Java_fp, intptr_t*)

#define DECLARE_INT_CPU_FEATURE_CONSTANT(id, name) GENERATE_VM_INT_CONSTANT_ENTRY(VM_Version::CPU_##id)
#define DECLARE_INT_CPU_FEATURE_CONSTANT(id, name, bit) GENERATE_VM_INT_CONSTANT_ENTRY(VM_Version::CPU_##id)
#define VM_INT_CPU_FEATURE_CONSTANTS CPU_FEATURE_FLAGS(DECLARE_INT_CPU_FEATURE_CONSTANT)

#endif
Expand All @@ -1037,7 +1037,7 @@
declare_constant(frame::interpreter_frame_sender_sp_offset) \
declare_constant(frame::interpreter_frame_last_sp_offset)

#define DECLARE_LONG_CPU_FEATURE_CONSTANT(id, name) GENERATE_VM_LONG_CONSTANT_ENTRY(VM_Version::CPU_##id)
#define DECLARE_LONG_CPU_FEATURE_CONSTANT(id, name, bit) GENERATE_VM_LONG_CONSTANT_ENTRY(VM_Version::CPU_##id)
#define VM_LONG_CPU_FEATURE_CONSTANTS \
CPU_FEATURE_FLAGS(DECLARE_LONG_CPU_FEATURE_CONSTANT)

Expand Down
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