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82e900e
move synthesis naming to a common naming utility so all synthesizers …
desmonddak Apr 17, 2026
85f88ce
dart 3.11 parameter_assignments pickiness
desmonddak Apr 17, 2026
b1de1e5
Merge branch 'main' into central_naming
desmonddak Apr 17, 2026
b7087c4
conflict resolved and dart format . works
desmonddak Apr 17, 2026
4a55214
properly assign naming spaces for instances vs signals
desmonddak Apr 18, 2026
ed7be36
format issue
desmonddak Apr 18, 2026
ab09aed
Controllable enforcement of signal vs instance name uniqueness.
desmonddak Apr 19, 2026
520d280
Refactored to Namer class. No external API changes for ROHD
desmonddak Apr 19, 2026
61d0319
signal registry
desmonddak Apr 20, 2026
becdb36
module context name uniquification instead of signal/instance split
desmonddak May 1, 2026
a86f80c
Merge branch 'main' into central_naming
desmonddak May 3, 2026
d5904a6
cleanup of port vs signal name assumptions, constant merging and sign…
desmonddak May 3, 2026
6dfe0f9
simplified forModule, improved code doc
desmonddak May 12, 2026
3c90e5d
more coverage for Namer
desmonddak May 12, 2026
c59e283
feat(interface_struct): register port groups from Interface.connectIO
desmonddak May 21, 2026
78ceb13
dart v3.12 analysis
desmonddak May 21, 2026
722627c
feat(interface_struct): add asStruct option to addPairInterfacePorts/…
desmonddak May 22, 2026
8fbb3f2
restored recursive interface reduction
desmonddak May 23, 2026
42fba62
canonical names at last, even in the comments
desmonddak Jun 12, 2026
6a41f8d
pesky override rule surfaced again on tutorials file
desmonddak Jun 12, 2026
139280f
new keyring-based installation for dart in codespaces
desmonddak Jun 12, 2026
62e4a2c
new keyring-based installation for dart in codespaces
desmonddak Jun 12, 2026
caecb02
keyring-style dart installation rather than holding keys
desmonddak Jun 14, 2026
089faf8
new dart analyzer failure with bad override
desmonddak Jun 14, 2026
e015889
Merge branch 'override-bug' into new-dart
desmonddak Jun 14, 2026
1232afb
Potential fix for pull request finding
desmonddak Jun 15, 2026
e558a4d
Orthogonalize: simplify Namer by removing instance name caching
desmonddak Jun 17, 2026
8ef6820
Fix orthogonalized Namer: remove stale instanceNameOf method
desmonddak Jun 17, 2026
1225df1
Clean DevTools extension analysis and formatting
desmonddak Jun 20, 2026
c8440c4
Keep DevTools extension changes on owning branches
desmonddak Jun 20, 2026
a87fa5c
added back pubkeys, and made a wget a fallback solution with loud war…
desmonddak Jun 21, 2026
d2760eb
Merge branch 'new-dart' into central_naming
desmonddak Jun 22, 2026
b7e46c0
Add instanceNameOf to Namer: cached instance-name lookup
desmonddak Jun 22, 2026
66a68f6
Remove duplicate instanceNameOf: now provided by central_naming
desmonddak Jun 22, 2026
0f13c7b
Move instanceNameOf stability test to central_naming
desmonddak Jun 22, 2026
8d8381a
Remove duplicate naming_consistency_test changes: now in central_naming
desmonddak Jun 22, 2026
319706b
Wire pickName through instanceNameOf for stable instance names
desmonddak Jun 22, 2026
11bc2cd
Add instance-signal namespace collision stability tests
desmonddak Jun 22, 2026
3b8a8a8
consistency in naming
desmonddak Jun 22, 2026
e1c01f7
Merge branch 'central_naming' into interface_struct
desmonddak Jun 22, 2026
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Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,6 @@ import '../../chapter_3/answers/helper.dart';
import '../../chapter_5/answers/full_subtractor.dart';

class FullSubtractorComb extends FullSubtractor {
@override
FullSubtractorComb(super.a, super.b, super.borrowIn) {
// Declare input and output
final a = input('a');
Expand Down
7 changes: 4 additions & 3 deletions lib/src/exceptions/logic/put_exception.dart
Original file line number Diff line number Diff line change
Expand Up @@ -9,10 +9,11 @@

import 'package:rohd/rohd.dart';

/// An exception that thrown when a [Logic] signal fails to `put`.
/// An exception that thrown when a [Logic] signal fails to [Logic.put].
class PutException extends RohdException {
/// Creates an exception for when a `put` fails on a `Logic` with [context] as
/// to where the
/// Creates an exception for when a [Logic.put] fails on a [Logic] with
/// [context] as to where the failure occurred and [message] describing the
/// failure.
PutException(String context, String message)
: super('Failed to put value on signal ($context): $message');
}
54 changes: 47 additions & 7 deletions lib/src/interfaces/interface.dart
Original file line number Diff line number Diff line change
Expand Up @@ -79,43 +79,81 @@ class Interface<TagType extends Enum> {
{Iterable<TagType>? inputTags,
Iterable<TagType>? outputTags,
Iterable<TagType>? inOutTags,
String Function(String original)? uniquify}) {
String Function(String original)? uniquify,
String? groupName}) {
uniquify ??= (original) => original;

// Derive the interface group name from the uniquify function.
// We probe with a sentinel to detect what the function adds.
// Supports prefix patterns (e.g. 'ace0_pcieRp_X') and suffix
// patterns (e.g. 'x_m', 'x_dti_a2f').
if (groupName == null) {
const sentinel = '\x00';
final probed = uniquify(sentinel);
if (probed.endsWith(sentinel)) {
// Prefix-based: uniquify('X') → 'prefix_X'
groupName = probed.substring(0, probed.length - 1);
} else if (probed.startsWith(sentinel)) {
// Suffix-based: uniquify('X') → 'X_suffix'
groupName = probed.substring(1);
}
}

// Helper to register the port group if we successfully extracted one.
void registerGroup(String portName) {
if (groupName != null && groupName.isNotEmpty) {
// Strip leading/trailing separators for a cleaner group name.
var trimmed = groupName;
if (trimmed.startsWith('_')) {
trimmed = trimmed.substring(1);
}
if (trimmed.endsWith('_')) {
trimmed = trimmed.substring(0, trimmed.length - 1);
}
if (trimmed.isNotEmpty) {
module.registerPortGroup(portName, trimmed);
}
}
}

if (inputTags != null) {
for (final port in getPorts(inputTags).values) {
final portName = uniquify(port.name);
port <=
(port is LogicArray
? module.addInputArray(
uniquify(port.name),
portName,
srcInterface.port(port.name),
dimensions: port.dimensions,
elementWidth: port.elementWidth,
numUnpackedDimensions: port.numUnpackedDimensions,
)
: module.addInput(
uniquify(port.name),
portName,
srcInterface.port(port.name),
width: port.width,
));
registerGroup(portName);
}
}

if (outputTags != null) {
for (final port in getPorts(outputTags).values) {
final portName = uniquify(port.name);
final output = (port is LogicArray
? module.addOutputArray(
uniquify(port.name),
portName,
dimensions: port.dimensions,
elementWidth: port.elementWidth,
numUnpackedDimensions: port.numUnpackedDimensions,
)
: module.addOutput(
uniquify(port.name),
portName,
width: port.width,
));
output <= port;
srcInterface.port(port.name) <= output;
registerGroup(portName);
}
}

Expand All @@ -131,20 +169,22 @@ class Interface<TagType extends Enum> {
port, 'LogicNet must be used for inOut ports.');
}

final portName = uniquify(port.name);
port <=
(port is LogicArray
? module.addInOutArray(
uniquify(port.name),
portName,
srcInterface.port(port.name),
dimensions: port.dimensions,
elementWidth: port.elementWidth,
numUnpackedDimensions: port.numUnpackedDimensions,
)
: module.addInOut(
uniquify(port.name),
portName,
srcInterface.port(port.name),
width: port.width,
));
registerGroup(portName);
}
}
}
Expand Down
40 changes: 40 additions & 0 deletions lib/src/interfaces/interface_structure.dart
Original file line number Diff line number Diff line change
@@ -0,0 +1,40 @@
// Copyright (C) 2026 Intel Corporation
// SPDX-License-Identifier: BSD-3-Clause
//
// interface_structure.dart
// A LogicStructure that represents a group of interface ports.
//
// 2026 May
// Author: ROHD Contributors

import 'package:meta/meta.dart';
import 'package:rohd/rohd.dart';

/// A [LogicStructure] created from a group of [Interface] ports.
///
/// This enables [Interface] ports grouped by direction to be represented as
/// a single `typedef struct packed` in SystemVerilog, rather than individual
/// flat signals.
///
/// The [interfaceTypeName] is used to derive the SV typedef name when
/// generating struct-typed output.
@internal
class InterfaceStructure extends LogicStructure {
/// The type name to use for the SV struct typedef, derived from the
/// interface class name.
final String interfaceTypeName;

/// Creates an [InterfaceStructure] from a list of [Logic] elements.
InterfaceStructure(
super.elements, {
required this.interfaceTypeName,
super.name,
});

@override
InterfaceStructure clone({String? name}) => InterfaceStructure(
elements.map((e) => e.clone(name: e.name)),
interfaceTypeName: interfaceTypeName,
name: name ?? this.name,
);
}
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