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enhancementNew feature or requestNew feature or requestStatus: Open.#647 In intel/rohd;Combinational loops can cause stack overflow in SystemVerilog synthesizer stack
bugSomething isn't workingSomething isn't workingStatus: Open.#641 In intel/rohd;Enable
unsafe_variancecheck inanalysis_options.yamlenhancementNew feature or requestNew feature or requestStatus: Open.#633 In intel/rohd;Better handling for
LogicStructures inPipelinesenhancementNew feature or requestNew feature or requestStatus: Open.#632 In intel/rohd;Allow assignment merging in SystemVerilog between packed arrays and non-arrays when legal
enhancementNew feature or requestNew feature or requestStatus: Open.#619 In intel/rohd;Propagate types through some operations
enhancementNew feature or requestNew feature or requestStatus: Open.#615 In intel/rohd;A type-safe mechanism to connect
PairInterfacesenhancementNew feature or requestNew feature or requestStatus: Open.#613 In intel/rohd;SystemVerilog.definitionParametersdoes not enforce uniqueness with other namesbugSomething isn't workingSomething isn't workingStatus: Open.#611 In intel/rohd;Module.uniqueInstanceNamenot enforced as reserved name inSynthstackbugSomething isn't workingSomething isn't workingStatus: Open.#610 In intel/rohd;Expose references to primitive inputs
enhancementNew feature or requestNew feature or requestStatus: Open.#609 In intel/rohd;abs() produces a complex name
enhancementNew feature or requestNew feature or requestStatus: Open.#608 In intel/rohd;Ability to control displayed radix of constants
enhancementNew feature or requestNew feature or requestStatus: Open.#601 In intel/rohd;