Netlist synthesizer

README.md

@@ -44,8 +44,8 @@ You can also open this repository in a GitHub Codespace to run the example in yo
 - Easy **IP integration** and **interfaces**; using an IP is as easy as an import.  Reduces tedious, redundant, and error prone aspects of integration
 - **Simple and fast build**, free of complex build systems and EDA vendor tools
 - Can use the excellent pub.dev **package manager** and all the packages it has to offer
-- Built-in event-based **fast simulator** with **4-value** (0, 1, X, and Z) support and a **waveform dumper** to .vcd file format
-- Conversion of modules to equivalent, human-readable, structurally similar **SystemVerilog** for integration or downstream tool consumption
+- Built-in event-based **fast simulator** with **4-value** (0, 1, X, and Z) support and a **waveform capture service** to .vcd file format
+- Conversion of modules to equivalent, human-readable, structurally similar **SystemVerilog** for integration or downstream tool consumption via **SvService**
 - **Run-time dynamic** module port definitions (numbers, names, widths, etc.) and internal module logic, including recursive module contents
 - Leverage the [ROHD Hardware Component Library (ROHD-HCL)](https://github.com/intel/rohd-hcl) with reusable and configurable design and verification components.
 - Simple, free, **open source tool stack** without any headaches from library dependencies, file ordering, elaboration/analysis options, +defines, etc.

benchmark/many_submodules_benchmark.dart

@@ -33,7 +33,7 @@ class ManySubmodulesBenchmark extends AsyncBenchmarkBase {
   Future<void> run() async {
     final dut = ManySubmodulesModule(Logic(), numSubModules: 10000);
     await dut.build();
-    dut.generateSynth();
+    SvService(dut).synthOutput;
   }
 }
 

benchmark/wave_dump_benchmark.dart

@@ -56,7 +56,7 @@ class WaveDumpBenchmark extends AsyncBenchmarkBase {
     _mod = _ModuleToDump(Logic(), _clk);
     await _mod.build();
 
-    WaveDumper(_mod, outputPath: _vcdTemporaryPath);
+    WaveformService(_mod, outputPath: _vcdTemporaryPath);
 
     await Simulator.run();
 

doc/tutorials/chapter_2/helper.dart

@@ -13,7 +13,8 @@ import 'package:rohd/rohd.dart';
 
 Future<void> displaySystemVerilog(Module mod) async {
   await mod.build();
-  print('\nYour System Verilog Equivalent Code: \n ${mod.generateSynth()}');
+  print('\nYour System Verilog Equivalent Code: \n'
+      '${SvService(mod).synthOutput}');
 }
 
 class LogicInitialization extends Module {

doc/tutorials/chapter_3/answers/exercise_sv.dart

@@ -33,7 +33,7 @@ void main() async {
   await fSub.build();
 
   // ignore: avoid_print
-  print(fSub.generateSynth());
+  print(SvService(fSub).synthOutput);
 
   test('should return 0 when a and b equal 1', () async {
     a.put(1);

doc/tutorials/chapter_3/full_adder.dart

@@ -77,5 +77,5 @@ void main() async {
   final mod = FullAdderModule(a, b, cIn, faOps);
   await mod.build();
 
-  print(mod.generateSynth());
+  print(SvService(mod).synthOutput);
 }

doc/tutorials/chapter_4/answers/exercise_1_sv.dart

@@ -10,7 +10,7 @@ void main() async {
   final mod = NBitAdder(a, b);
   await mod.build();
 
-  print(mod.generateSynth());
+  print(SvService(mod).synthOutput);
 
   test('should return 255 when both inputs are added', () {
     a.put(127);

doc/tutorials/chapter_4/answers/exercise_2_sv.dart

@@ -9,7 +9,7 @@ void main() async {
 
   final mod = NBitSubtractor(a, b);
   await mod.build();
-  print(mod.generateSynth());
+  print(SvService(mod).synthOutput);
 
   test('should return 5 when a is 25 and b is 20', () {
     a.put(25);

doc/tutorials/chapter_4/basic_generation_sv.dart

@@ -78,7 +78,7 @@ void main() async {
 
   await nbitAdder.build();
 
-  print(nbitAdder.generateSynth());
+  print(SvService(nbitAdder).synthOutput);
 
   test('should return 10 when both inputs are 5.', () async {
     a.put(5);

doc/tutorials/chapter_5/answers/full_adder.dart

@@ -49,7 +49,7 @@ void main() async {
   final mod = FullAdder(a: a, b: b, carryIn: cIn);
   await mod.build();
 
-  print(mod.generateSynth());
+  print(SvService(mod).synthOutput);
 
   test('should return true if result sum similar to truth table.', () async {
     for (var i = 0; i <= 1; i++) {

doc/tutorials/chapter_5/answers/full_subtractor.dart

@@ -44,7 +44,7 @@ Future<void> main() async {
 
   await diff.build();
 
-  print(diff.generateSynth());
+  print(SvService(diff).synthOutput);
 
   test('should return true if results matched truth table', () async {
     for (var i = 0; i <= 1; i++) {

doc/tutorials/chapter_5/answers/n_bit_subtractor.dart

@@ -36,7 +36,7 @@ Future<void> main() async {
   final mod = NBitFullSubtractor(a, b);
   await mod.build();
 
-  print(mod.generateSynth());
+  print(SvService(mod).synthOutput);
 
   test('should return 1 when a is 8 and b is 7.', () {
     a.put(8);

doc/tutorials/chapter_5/n_bit_adder.dart

@@ -79,7 +79,7 @@ void main() async {
 
   await nbitAdder.build();
 
-  // print(nbitAdder.generateSynth());
+  // print(SvService(nbitAdder).synthOutput);
 
   test('should return 20 when A and B perform add.', () async {
     a.put(15);

doc/tutorials/chapter_6/answers/exercise_2_n_bit_subtractor.dart

@@ -7,7 +7,6 @@ import '../../chapter_3/answers/helper.dart';
 import '../../chapter_5/answers/full_subtractor.dart';
 
 class FullSubtractorComb extends FullSubtractor {
-  @override
   FullSubtractorComb(super.a, super.b, super.borrowIn) {
     // Declare input and output
     final a = input('a');

doc/tutorials/chapter_7/answers/exercise_1_d_flip_flop.dart

@@ -44,7 +44,7 @@ Future<void> main() async {
     final dff = DFlipFlop(data, reset, clk);
     await dff.build();
 
-    print(dff.generateSynth());
+    print(SvService(dff).synthOutput);
 
     data.inject(1);
     reset.inject(1);
@@ -60,7 +60,7 @@ Future<void> main() async {
 
     unawaited(Simulator.run());
 
-    WaveDumper(dff,
+    WaveformService(dff,
         outputPath: 'doc/tutorials/chapter_7/answers/d_flip_flop.vcd');
 
     printFlop('Before');

doc/tutorials/chapter_7/shift_register.dart

@@ -69,7 +69,7 @@ void main() async {
     // kick-off the simulator, but we don't want to wait
     unawaited(Simulator.run());
 
-    WaveDumper(shiftReg,
+    WaveformService(shiftReg,
         outputPath: 'doc/tutorials/chapter_7/shift_register.vcd');
 
     printFlop('Before');

doc/tutorials/chapter_8/answers/exercise_1_spi.dart

@@ -139,7 +139,7 @@ void main() async {
 
   await tb.build();
 
-  print(tb.generateSynth());
+  print(SvService(tb).synthOutput);
 
   testInterface.cs.inject(0);
   testInterface.sdi.inject(0);
@@ -163,7 +163,7 @@ void main() async {
   Simulator.setMaxSimTime(100);
   unawaited(Simulator.run());
 
-  WaveDumper(peri, outputPath: 'doc/tutorials/chapter_8/spi-new.vcd');
+  WaveformService(peri, outputPath: 'doc/tutorials/chapter_8/spi-new.vcd');
 
   await drive(LogicValue.ofString('01010101'));
 }

doc/tutorials/chapter_8/answers/exercise_2_toycapsule_fsm.dart

@@ -49,13 +49,13 @@ Future<void> main(List<String> args) async {
   final toyCap = ToyCapsuleFSM(clk, reset, dispenseBtn, coin);
   await toyCap.build();
 
-  print(toyCap.generateSynth());
+  print(SvService(toyCap).synthOutput);
 
   toyCap.toyCapsuleStateMachine.generateDiagram();
 
   reset.inject(1);
 
-  WaveDumper(toyCap, outputPath: 'toyCapsuleFSM.vcd');
+  WaveformService(toyCap, outputPath: 'toyCapsuleFSM.vcd');
 
   Simulator.setMaxSimTime(100);
   Simulator.registerAction(25, () {

doc/tutorials/chapter_8/answers/exercise_3_pipeline.dart

@@ -34,14 +34,14 @@ void main(List<String> args) async {
     final pipe = Pipeline4Stages(clk, reset, a);
     await pipe.build();
 
-    // print(pipe.generateSynth());
+    // print(SvService(pipe).synthOutput);
 
     a.inject(5);
     reset.inject(1);
 
     Simulator.registerAction(10, () => reset.put(0));
 
-    WaveDumper(pipe, outputPath: 'answer_1.vcd');
+    WaveformService(pipe, outputPath: 'answer_1.vcd');
 
     Simulator.registerAction(50, () async {
       // stage 4 / result: 30 + (30 * 3) = 120

doc/tutorials/chapter_8/carry_save_multiplier.dart

@@ -108,7 +108,7 @@ void main() async {
   reset.inject(1);
 
   // Attach a waveform dumper so we can see what happens.
-  WaveDumper(csm, outputPath: 'csm.vcd');
+  WaveformService(csm, outputPath: 'csm.vcd');
 
   Simulator.registerAction(10, () {
     reset.inject(0);

doc/tutorials/chapter_8/counter_interface.dart

@@ -63,9 +63,9 @@ Future<void> main() async {
 
   await counter.build();
 
-  print(counter.generateSynth());
+  print(SvService(counter).synthOutput);
 
-  WaveDumper(counter,
+  WaveformService(counter,
       outputPath: 'doc/tutorials/chapter_8/counter_interface.vcd');
   Simulator.registerAction(25, () {
     intf.en.put(1);

doc/tutorials/chapter_8/oven_fsm.dart

@@ -192,7 +192,7 @@ Future<void> main({bool noPrint = false}) async {
 
   // Attach a waveform dumper so we can see what happens.
   if (!noPrint) {
-    WaveDumper(oven, outputPath: 'doc/tutorials/chapter_8/oven.vcd');
+    WaveformService(oven, outputPath: 'doc/tutorials/chapter_8/oven.vcd');
   }
 
   if (!noPrint) {

doc/tutorials/chapter_9/rohd_vf_example/lib/counter.dart

@@ -11,19 +11,17 @@ class MyCounterInterface extends Interface<CounterDirection> {
 
   final int width;
   MyCounterInterface({this.width = 8}) {
-    setPorts(
-        [Logic.port('en'), Logic.port('reset')], [CounterDirection.inward]);
+    setPorts([Port('en'), Port('reset')], [CounterDirection.inward]);
 
     setPorts([
-      Logic.port('val', width),
+      Port('val', width),
     ], [
       CounterDirection.outward
     ]);
 
-    setPorts([Logic.port('clk')], [CounterDirection.misc]);
+    setPorts([Port('clk')], [CounterDirection.misc]);
   }
 
-  @override
   MyCounterInterface clone() => MyCounterInterface(width: width);
 }
 
@@ -38,9 +36,10 @@ class MyCounter extends Module {
   late final MyCounterInterface counterintf;
 
   MyCounter(MyCounterInterface intf) : super(name: 'counter') {
-    counterintf = addInterfacePorts(counterintf,
-        inputTags: {CounterDirection.inward, CounterDirection.misc},
-        outputTags: {CounterDirection.outward});
+    counterintf = MyCounterInterface(width: intf.width)
+      ..connectIO(this, intf,
+          inputTags: {CounterDirection.inward, CounterDirection.misc},
+          outputTags: {CounterDirection.outward});
 
     _buildLogic();
   }

doc/tutorials/chapter_9/rohd_vf_example/lib/rohd_vf_example.dart

@@ -315,7 +315,7 @@ Future<void> main({Level loggerLevel = Level.FINER}) async {
   await tb.counter.build();
 
   // dump wave here
-  WaveDumper(tb.counter);
+  WaveformService(tb.counter);
 
   // Set a maximum simulation time so it doesn't run forever
   Simulator.setMaxSimTime(300);

doc/tutorials/chapter_9/rohd_vf_example/pubspec.yaml

@@ -8,10 +8,14 @@ environment:
 
 # Add regular dependencies here.
 dependencies:
-  rohd: ^0.4.2
-  rohd_vf: ^0.4.1
+  rohd: ^0.6.0
+  rohd_vf: ^0.6.0
   logging: ^1.0.1
 
+dependency_overrides:
+  rohd:
+    path: ../../../../
+
 dev_dependencies:
   lints: ^2.0.0
   test: ^1.21.0

example/example.dart

@@ -11,35 +11,16 @@
 // allow `print` messages (disable lint):
 // ignore_for_file: avoid_print
 
-// Import necessary dart packages for this file.
+// Import necessary dart pacakges for this file.
 import 'dart:async';
 
 // Import the ROHD package.
 import 'package:rohd/rohd.dart';
 
-// Define a class Counter that extends ROHD's abstract Module class.
-class Counter extends Module {
-  // For convenience, map interesting outputs to short variable names for
-  // consumers of this module.
-  Logic get val => output('val');
-
-  // This counter supports any width, determined at run-time.
-  final int width;
-
-  Counter(Logic en, Logic reset, Logic clk,
-      {this.width = 8, super.name = 'counter'}) {
-    // Register inputs and outputs of the module in the constructor.
-    // Module logic must consume registered inputs and output to registered
-    // outputs.
-    en = addInput('en', en);
-    reset = addInput('reset', reset);
-    clk = addInput('clk', clk);
-    addOutput('val', width: width);
-
-    // We can use the `flop` function to automate creation of a `Sequential`.
-    val <= flop(clk, reset: reset, en: en, val + 1);
-  }
-}
+// Re-export the Counter module from the library examples so that
+// existing tests that `import 'example/example.dart'` still see it.
+import 'package:rohd/src/examples/oven_fsm_modules.dart' show Counter;
+export 'package:rohd/src/examples/oven_fsm_modules.dart' show Counter;
 
 // Let's simulate with this counter a little, generate a waveform, and take a
 // look at generated SystemVerilog.
@@ -61,7 +42,7 @@ Future<void> main({bool noPrint = false}) async {
 
   // Let's see what this module looks like as SystemVerilog, so we can pass it
   // to other tools.
-  final systemVerilogCode = counter.generateSynth();
+  final systemVerilogCode = SvService(counter).synthOutput;
   if (!noPrint) {
     print(systemVerilogCode);
   }
@@ -70,14 +51,15 @@ Future<void> main({bool noPrint = false}) async {
 
   // Attach a waveform dumper so we can see what happens.
   if (!noPrint) {
-    WaveDumper(counter);
+    WaveformService(counter);
   }
 
   // Let's also print a message every time the value on the counter changes,
   // just for this example to make it easier to see before we look at waves.
   if (!noPrint) {
-    counter.val.changed
-        .listen((e) => print('@${Simulator.time}: Value changed: $e'));
+    counter.val.changed.listen(
+      (e) => print('@${Simulator.time}: Value changed: $e'),
+    );
   }
 
   // Start off with a disabled counter and asserting reset at the start.
@@ -115,7 +97,9 @@ Future<void> main({bool noPrint = false}) async {
 
   // We can take a look at the waves now.
   if (!noPrint) {
-    print('To view waves, check out waves.vcd with a waveform viewer'
-        ' (e.g. `gtkwave waves.vcd`).');
+    print(
+      'To view waves, check out waves.vcd with a waveform viewer'
+      ' (e.g. `gtkwave waves.vcd`).',
+    );
   }
 }