CMOS NAND Gate design using Cadence Virtuoso including schematic design, simulation and layout verification (DRC, LVS REX).

This project involves designing a digital dice display system using a 3x3 grid of LEDs (A, B, C, D, E, F, G, H, J) and utilizing only NAND gates to achieve the desired logic. The display corresponds to a 4-bit binary input, with each combination lighting up specific LEDs to represent different dice patterns

The focus is on familiarization with the design environment and compiling a simple logic design.

Designing a logical Nand Gate utilising perceptron algorithm