Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

🧮 Explore core mathematical functions for VIVA, enhancing research in emotional dynamics, consciousness, and information theory.

Single-cycle RISC CPU with 5-stage pipeline and multiplication & division support based on RV32I, verified & deployed rotating leds on Genesys2.

The E203 Hbirdv2 RISC-V Core transplanted on Genesys2

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

Very simple CPU(4 instructions) deployed & verified on FPGA Genesys2.

Hbird SDK, with more examples and Genesys2 supported

Predict future robot states and task progress using a video-generative value model to improve reinforcement learning performance.