A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding
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May 20, 2022 - Verilog
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forwarding-unit
Here are 12 public repositories matching this topic...
Verilog Implementation of an ARM LEGv8 CPU
arm verilog xilinx isa vivado hazard-detection ldr pipeline-cpu single-cycle hennessy patterson legv8-arm multi-cycle arm-legv8-simulator forwarding-unit
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Oct 3, 2018 - Verilog
Final Project of the Computer Architecture (ICOM4215) course, Spring 2023. The project documents the journey of three students learning the basics of the vast world of FPGAs and hardware design in general. Here We designed a SPARC-Based Processor in Verilog :D
fpga hardware verilog instruction-semantics computer-architecture forwarding-unit uprm sparcv8 icom-4215 sparc-architecture
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Sep 14, 2023 - Verilog
A pipelined MIPS processor implemented in Verilog, featuring hazard detection and forwarding.
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Sep 13, 2025 - Verilog
ARM processor pipeline implementation. Featuring hazard unit, forwarding unit, SRAM & cache memory.
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Feb 1, 2024 - Verilog
A 32-bit Arm Processor Using Verilog HDL With Hazard Detection, Forwarding Unit, SRAM Memory & A 2-Way Set-Associative Cache.
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Jul 22, 2021 - Verilog
SystemVerilog RTL implementation of a 5-stage pipelined RISC-V processor with hazard detection, forwarding, stall/flush control, simulation verification, and Vivado synthesis.
fpga simulation verification xilinx synthesis vivado systemverilog computer-architecture hazard-detection risc-v digital-design rv32i waveform-analysis processor-design cpu-design forwarding-unit rtl-design hardware-design pipelined-processor
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May 16, 2026 - SystemVerilog
Verilog Implementation of an ARM LEGv8 CPU
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Aug 14, 2018 - Verilog
ARM processor implementation, hazard unit, forwarding unit, SRAM & cache memory.
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Jul 24, 2023 - Verilog
The design of modules to reduce pipeline Hazards, as well as the MIPS processor architecture. It implements some instruction set, instruction and data memory, 32 general- purpose registers, an Arithmetic Logical Unit (ALU) for basic operation, a forwarding unit and hazards detecting unit.
mips computer-architecture hazard-detection mips-architecture mips32 nirma-university forwarding-unit control-hazards 5-stage-pipelined-processor hazard-mitigation
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Oct 27, 2024 - Verilog
Verilog HDL implementation of a 5-stage pipelined RISC-V processor with Hazard Detection and Forwarding Unit verified using EDA playground and EPWave.
verilog computer-architecture hazard-detection pipeline-processor risc-v forwarding-unit eda-playground
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May 25, 2026 - Verilog
Design for a 6-stage pipeline processor that supports load, store, jump, or, beq, bne and andi instructions. Additional support for handling data hazards through stalls, flushing and forwarding.
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May 31, 2026 - Verilog
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