This repository was archived by the owner on Jan 16, 2022. It is now read-only.

Name		Name	Last commit message	Last commit date
Latest commit History 21 Commits
Arduino		Arduino
.gitignore		.gitignore
ArithmeticLogicUnit.v		ArithmeticLogicUnit.v
BIOS.v		BIOS.v
BinaryCodedDecimal.v		BinaryCodedDecimal.v
ControlUnit.v		ControlUnit.v
Datapath.v		Datapath.v
DeBounce.v		DeBounce.v
Display7.v		Display7.v
Divisor.v		Divisor.v
HardDisk.v		HardDisk.v
IN.v		IN.v
LCD_Display.v		LCD_Display.v
Memory.v		Memory.v
MemoryData.v		MemoryData.v
MemoryInstructions.v		MemoryInstructions.v
Memory_HD.v		Memory_HD.v
OUT_IN.v		OUT_IN.v
OUT_LCD.v		OUT_LCD.v
OUT_TEST.v		OUT_TEST.v
Processor.v		Processor.v
ProgramCounter.v		ProgramCounter.v
README.md		README.md
RegisterFile.v		RegisterFile.v
Reset_Delay.v		Reset_Delay.v
SO_control.v		SO_control.v
Thiago.restore.rpt		Thiago.restore.rpt
Thiago.v		Thiago.v
Thiago_assignment_defaults.qdf		Thiago_assignment_defaults.qdf
assignment_defaults.qdf		assignment_defaults.qdf
qar_info.json		qar_info.json

Repository files navigation

ProcessadorVerilog

No description, website, or topics provided.

0 stars

0 watching