16bit_Comparator_SystemVerilog_Verification

This repository contains the design and verification environment for the 16-bit comparator, implemented in SystemVerilog.

Overview

The 16-bit comparator is a digital circuit designed to compare two 16-bit binary numbers. It provides three outputs to indicate the relationship between the two numbers:

• A < B: High (1) if A is less than B.
• A = B: High (1) if A is equal to B.
• A > B: High (1) if A is greater than B.

Files

Description of each file in the repository:

Design Files

• comp.v: Verilog implementation of the 16-bit comparator.

Testbench and Verification Files

• testbench.sv: Top-level module that integrates the 32-bit comparator and the testbench.
  
• comp_tb.sv: Testbench module for the 32-bit comparator.
  
• comp_int.sv: Interface definition for the 32-bit comparator.
  
• comp_env.sv: Environment setup for the comparator testbench.
  
• comp_cov.sv: Coverage analysis module for the comparator.
  
• comp_ckr.sv: Checker module to validate the comparator functionality.
  
• comp_mon.sv: Monitor module to observe and report the comparator's behavior.
  
• comp_bfm.sv: Bus Functional Model (BFM) for generating and managing transactions.
  
• comp_gen.sv: Random test case generator for the comparator.
  
• comp_cfg.sv: Configuration class for setting up the test environment.
  
• comp_tx.sv: Transaction class for handling and generating input values.
  

Input Vectors of the 16bit_Comparator

Output Result