Hermes is a hardware-accelerated market making engine built entirely on an FPGA. It receives live CME MDP 3.0 market data directly from Ethernet, reconstructs a real-time order book in hardware, computes fair value from market microstructure signals, and submits quotes back to the exchange over iLink3/FIXP — all with deterministic latency and no CPU in the execution path. Built on the Digilent Arty A7-35T (Artix-7 XC7A35T).
CME MDP 3.0 Market Data
↓
Ethernet / IPv4 / UDP
↓
MDP 3.0 Parser
↓
10-Level Order Book
↓
Market Making Engine
(VWAP + OFI + Inventory Skew)
↓
Risk Engine / Quote Logic
↓
iLink3 / FIXP Order Entry
↓
TCP / IP / Ethernet
Incoming market data is parsed directly on the FPGA. Book state updates in real time, fair value is recomputed continuously, and quotes are serialized back onto the wire as exchange-native order entry messages. The full receive-to-transmit trading path runs entirely in hardware.
A hardware parser for CME MDP 3.0 multicast market data supports incremental refresh, snapshot refresh, and trade summary messages.
Updates feed into an on-chip 10-level bid/ask order book, maintained in real time. The book tracks price and size at each level, validates packet sequencing, detects feed gaps, and resynchronizes from snapshot data when needed.
The quoting engine computes fair value using multiple market signals:
- VWAP-weighted mid price across configurable depth levels
- Order Flow Imbalance (OFI) derived from aggressor-side trades
- Inventory skew based on current net position
Strategy behavior includes configurable quote size and spread, inventory-aware quote skewing, directional quoting during strong one-sided flow, and periodic quote refresh to avoid stale resting orders.
Pre-trade risk checks execute inline in hardware before any order is transmitted:
- Maximum net position limits
- Order rate limiting
- Realized and unrealized P&L monitoring
- Quote suppression on market-data desynchronization or risk breach
Native CME iLink3 / FIXP order entry is implemented directly in RTL. The transmit path handles FIXP session negotiation, sequence tracking, heartbeat messaging, NewOrderSingle, and OrderCancelRequest. Orders are serialized directly into TCP/IP/Ethernet frames with no software networking stack in the path.
The hardware networking stack includes RTL implementations of:
- Ethernet, ARP, IPv4, UDP, TCP, ICMP
- MDIO PHY configuration (DP83848J)
Current hardware runs over 100 Mbps MII, with RGMII support implemented for future gigabit PHY hardware.
The design is organized as a pipelined datapath with separate tx and rx clock domains (both 25 MHz, asynchronous). All cross-domain signals use toggle-based CDC. Key modules:
Receive path: mii_rx → eth_parser → ip_parser → tcp_rx / udp_rx → ilink_rx / mdp_parser
Transmit path: ilink_tx / icmp_tx / arp_tx → tcp_tx / udp_tx → ip_tx → eth_tx → mii_tx
Trading logic: mdp_parser → order_book → mm_core → mm_top → ilink_tx
mm_top is the top-level orchestrator. It manages the TCP session state machine, iLink handshake sequencing, TX arbitration across all protocol engines, and wires the trading pipeline together.
Verified at two levels:
Simulation: Module-level and full-system SystemVerilog testbenches covering market data parsing, order book updates, snapshot and incremental replay, TCP session establishment, and end-to-end quote generation.
Hardware-in-the-loop: Python test scripts drive the full FPGA over live Ethernet — sending MDP 3.0 multicast snapshots and incremental refresh, completing the iLink3 FIXP session handshake (Negotiate → NegotiationResponse → Establish → EstablishmentAck), and verifying that the FPGA emits valid bid/ask NewOrderSingle messages in response. The design is also structured for connectivity testing against CME certification environments using replayed MDP3 traffic.
| Component | Value |
|---|---|
| FPGA | Xilinx Artix-7 XC7A35T |
| Board | Digilent Arty A7-35T |
| PHY | TI DP83848J |
| Interface | MII (100 Mbps), RGMII-ready |
| Toolchain | Vivado 2025.2 |