Prepare qcom-next based on tag 'Linux 7.1-rc4' of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git#604
Open
sgaud-quic wants to merge 848 commits into
Conversation
…ap_attach() Commit c7d8100 introduced a brace-less if that skips the dma_buf_map_attachment_unlocked() call when sess->coherent is true, leaving 'table' uninitialized. The unconditional IS_ERR(table) check that follows does not catch NULL, so execution continues with a NULL sg_table, causing a level-0 translation fault when the sgl pointer is dereferenced. Remove the guard; the mapping is always needed to obtain DMA addresses consumed by the rest of the function. Signed-off-by: Anandu Krishnan E <[email protected]>
…-reg The pm4125 PMIC uses a different USB VBUS register layout than pm8150b. It uses a 2-bit VBOOST voltage selector supporting output voltages of 4.25 V, 4.5 V, 4.75 V and 5.0 V, instead of a current-limit selector. Move qcom,pm4125-vbus-reg from the pm8150b fallback items list into the standalone enum since the driver handles it with its own match-data and register layout. Make regulator-min/max-microamp conditional so they are only required for current-limit variants (pm8150b, pm6150, pm7250b, pmi632). Add an if/then condition for qcom,pm4125-vbus-reg requiring regulator-min/ max-microvolt instead, and update the pm4125 example accordingly. Signed-off-by: Rakesh Kota <[email protected]>
The PM4125 PMIC uses a different register layout for USB VBUS control compared to PM8150B. On PM4125, CMD_OTG is at offset 0x50, OTG_CFG is at 0x56, and offset 0x52 is a 2-bit VBOOST voltage selector rather than a current-limit selector. Introduce per-compatible regulator descriptor data to accommodate these differences. This keeps the existing PM8150B current-limit logic intact while adding a dedicated voltage-selector path for PM4125. Signed-off-by: Rakesh Kota <[email protected]>
Document shikra compatible for the True Random Number Generator. Link: https://lore.kernel.org/lkml/[email protected]/ Signed-off-by: Kuldeep Singh <[email protected]>
…ngine Document the crypto engine on the Shikra platform. Link:https://lore.kernel.org/lkml/[email protected]/ Signed-off-by: Kuldeep Singh <[email protected]>
Shikra bam dma engine support seven iommu entries. Increase maxItems property for iommus to pass dtbs_check errors. Link: https://lore.kernel.org/lkml/[email protected]/ Signed-off-by: Kuldeep Singh <[email protected]>
Document the Inline Crypto Engine (ICE) on the Shikra platform. Signed-off-by: Kuldeep Singh <[email protected]>
…sent Some clock controller descriptors do not provide any reset lines. Avoid registering a reset controller when desc->num_resets is zero by making the registration conditional. Signed-off-by: Imran Shaik <[email protected]>
Some Qualcomm clock controller descriptors may contain NULL entries in the clk_hws array. Skip such entries when registering clock hardware to avoid passing NULL pointers to the clock framework. Signed-off-by: Imran Shaik <[email protected]>
Add GCC LPASS clocks support for Qualcomm Shikra SoC. Signed-off-by: Imran Shaik <[email protected]>
The GCC LPASS clocks must be enabled to access audio core clock controller registers. Hence, mark them as critical on Qualcomm Shikra SoCs. Signed-off-by: Imran Shaik <[email protected]>
…ller Add device tree bindings for the Audio Core clock controller on Qualcomm Shikra SoC. Signed-off-by: Imran Shaik <[email protected]>
… SoC Add support for Audio core clock controller on Qualcomm Shikra SoC. Signed-off-by: Imran Shaik <[email protected]>
Shikra shares the same power domain topology as sm6125. Remove the dedicated shikra_rpmpds[] and update shikra_desc to reuse sm6125_rpmpds[] with RPM_SMD_LEVEL_TURBO_NO_CPR. Signed-off-by: Rakesh Kota <[email protected]>
The display, peripherals (touchpad/touchscreen/keypad), usb and their dependent device nodes are common to both Glymur and Mahua CRDs, so move them from glymur-crd.dts to glymur-crd.dtsi to enable code reuse. Link: https://lore.kernel.org/lkml/20260326-glymur-mahua-common-nodes-v1-1-12bb26920ea4@oss.qualcomm.com/ Signed-off-by: Gopikrishna Garmidi <[email protected]> Signed-off-by: Pradyot Kumar Nayak <[email protected]>
Add remoteproc PAS loader for ADSP and CDSP with its fastrpc nodes. Link: https://lore.kernel.org/lkml/[email protected]/ Signed-off-by: Sibi Sankar <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Pradyot Kumar Nayak <[email protected]>
Enable ADSP and CDSP on Glymur CRD board. Link: https://lore.kernel.org/lkml/[email protected]/ Signed-off-by: Sibi Sankar <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Pradyot Kumar Nayak <[email protected]>
Add LPASS macro codecs and LPASS TLMM pin controller on Qualcomm glymur. for proper sound support. Also add GPR(Generic Pack router) node along with APM(Audio Process Manager) and PRM(Proxy resource Manager) audio services. Link: https://lore.kernel.org/lkml/[email protected]/ Co-developed-by: Mohammad Rafi Shaik <[email protected]> Signed-off-by: Mohammad Rafi Shaik <[email protected]> Signed-off-by: Srinivas Kandagatla <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Pradyot Kumar Nayak <[email protected]>
Add the sound card of Glymur-crd board with the routing for speakers. Add device nodes for the sound support with WSA884x smart speakers and playback via speakers and recording via DMIC microphones. Link: https://lore.kernel.org/lkml/[email protected]/ Co-developed-by: Mohammad Rafi Shaik <[email protected]> Signed-off-by: Mohammad Rafi Shaik <[email protected]> Signed-off-by: Srinivas Kandagatla <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Pradyot Kumar Nayak <[email protected]>
…Glymur Add the device nodes for the multimedia clock controllers videocc, gpucc and gxclkctl. Link: https://lore.kernel.org/r/20260220-glymur_mmcc_dt_config-v1-1-e0e2f43a32af@oss.qualcomm.com Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Taniya Das <[email protected]> Signed-off-by: Pradyot Kumar Nayak <[email protected]>
Add the nodes to describe the GPU SMMU node. Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Rajendra Nayak <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Akhil P Oommen <[email protected]>
The Adreno X2 series GPU present in Glymur SoC belongs to the A8x family. It is a new HW IP with architectural improvements as well as different set of hw configs like GMEM, num SPs, Caches sizes etc. Add the GPU and GMU nodes to describe this hardware. Link: https://lore.kernel.org/all/[email protected]/ Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Akhil P Oommen <[email protected]>
The GPU does not throttle its speed automatically when it reaches high temperatures. Set up GPU cooling by throttling the GPU speed when it reaches 95°C. Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Manaf Meethalavalappu Pallikunhi <[email protected]> Signed-off-by: Akhil P Oommen <[email protected]>
…vice EC description Add description for the EC firmware running on Hamoa/Purwa and Glymur reference devices. List: https://lore.kernel.org/lkml/[email protected]/ Signed-off-by: Maya Matuszczyk <[email protected]> Co-developed-by: Sibi Sankar <[email protected]> Signed-off-by: Sibi Sankar <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Co-developed-by: Anvesh Jain P <[email protected]> Signed-off-by: Anvesh Jain P <[email protected]>
…nce devices Add Embedded controller driver support for Hamoa/Purwa/Glymur qualcomm reference boards. It handles fan control, temperature sensors, access to EC state changes and supports reporting suspend entry/exit to the EC. List: https://lore.kernel.org/lkml/[email protected]/ Co-developed-by: Maya Matuszczyk <[email protected]> Signed-off-by: Maya Matuszczyk <[email protected]> Signed-off-by: Sibi Sankar <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Acked-by: Konrad Dybcio <[email protected]> Tested-by: Akhil P Oommen <[email protected]> Co-developed-by: Anvesh Jain P <[email protected]> Signed-off-by: Anvesh Jain P <[email protected]>
Add lane_positions to the DPHY configuration struct. This data-field represents the physical positions of the data-lanes indexed by lane number. Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Bryan O'Donoghue <[email protected]>
Pass an array of data-lane polarities from controller to PHY. A true value means the lane polarity is inverted. Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Bryan O'Donoghue <[email protected]>
We need to identify which lane is the clock-lane as many different PHYs allow for a range of lanes, potentially any of the lanes to be the clock input lane on a PHY. Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Bryan O'Donoghue <[email protected]>
Specify the polarity of the clock lane in DPHY mode. When true this bool means the polarity is inverted. Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Bryan O'Donoghue <[email protected]>
Add a base schema initially compatible with x1e80100 to describe MIPI CSI2 PHY devices. The hardware can support both CPHY, DPHY and a special split-mode DPHY. We capture those modes as: - PHY_QCOM_CSI2_MODE_DPHY - PHY_QCOM_CSI2_MODE_CPHY - PHY_QCOM_CSI2_MODE_SPLIT_DPHY The CSIPHY devices have their own pinouts on the SoC as well as their own individual voltage rails. The need to model voltage rails on a per-PHY basis leads us to define CSIPHY devices as individual nodes. Two nice outcomes in terms of schema and DT arise from this change. 1. The ability to define on a per-PHY basis voltage rails. 2. The ability to require those voltage. We have had a complete bodge upstream for this where a single set of voltage rail for all CSIPHYs has been buried inside of CAMSS. Much like the I2C bus which is dedicated to Camera sensors - the CCI bus in CAMSS parlance, the CSIPHY devices should be individually modelled. Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Bryan O'Donoghue <[email protected]>
# Conflicts: # arch/arm64/boot/dts/qcom/kaanapali.dtsi
# Conflicts: # drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
# Conflicts: # Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml # drivers/remoteproc/qcom_q6v5_pas.c # drivers/soc/qcom/smem.c
Adding merge log file and topic_SHA1 file Signed-off-by: Salendarsingh Gaud <[email protected]>
Test Matrix
|
Test Matrix
|
Test Matrix
|
Test Matrix
|
Test Matrix
|
Test Matrix
|
|
Merge Check Failed: No CR Numbers Found Error: No Change Request numbers were found. Please add Change Request numbers to your pull request description in the format CRs-Fixed: 12345 or link GitHub issues that are associated with Change Requests. |
Test Matrix
|
|
Merge Check Failed: No CR Numbers Found Error: No Change Request numbers were found. Please add Change Request numbers to your pull request description in the format CRs-Fixed: 12345 or link GitHub issues that are associated with Change Requests. |
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Name SHA Commits
tech/bsp/clk eea3e98 11
tech/bsp/devfreq a0c2f21 6
tech/bsp/ec 643c24b 2
tech/bsp/soc-infra 20c09ce 3
tech/bsp/pinctrl 3f1acf8 1
tech/bsp/remoteproc a7b9b6d 10
tech/bus/peripherals 287f0f5 8
tech/bus/pci/all c266573 14
tech/bus/pci/phy aaf8ef1 4
tech/bus/usb/dwc 49ac8e0 2
tech/bus/usb/phy 8c7f91d 35
tech/debug/hwtracing 25c6a74 30
tech/pmic/misc ee32a8c 5
tech/mem/iommu 1fa98cb 5
tech/mm/audio/all cab3357 10
tech/mm/camss 147ae87 28
tech/mm/drm 2fbdd74 60
tech/mm/fastrpc e0ba718 9
tech/mm/phy 56ccbf4 1
tech/mm/video 8bbe314 36
tech/mm/gpu cee7794 5
tech/net/ath 850c3c0 15
tech/net/phy a3602e9 1
tech/net/bluetooth 9cca493 2
tech/pm/power 2d42c35 9
tech/pm/thermal 3f033cb 7
tech/security/crypto f030676 14
tech/security/ice 1564b82 25
tech/storage/phy cf1667f 1
tech/storage/all e254dae 1
tech/all/dt/qcs6490 58c1242 20
tech/all/dt/qcs9100 b51f0ee 18
tech/all/dt/qcs8300 ffd35fe 16
tech/all/dt/qcs615 9e2f111 9
tech/all/dt/agatti c828f10 1
tech/all/dt/hamoa 670d002 29
tech/all/dt/glymur 29aa2ab 25
tech/all/dt/kaanapali 33d3cd7 11
tech/all/dt/pakala fee7c34 8
tech/all/config ff67f6a 61
tech/overlay/dt bc66459 47
tech/all/workaround d15f5a1 15
tech/mproc/all 0aa90b7 3
tech/noup/debug/all d2b684d 25
tech/hwe/unoq b2ea57b 5
early/hwe/shikra/drivers b26f0d6 86
early/hwe/shikra/dt 919fd6c 61
Issues:
Closed :