DNM: do-not-merge: remoteproc: qcom_q6v5: panic on watchdog/fatal if dump_conf not set#591
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The Shikra SoM is a compact compute module integrating the SoC and essential components optimized for IoT applications, designed to mount on carrier boards. Shikra supports three SoM variants: two retail options (with and without modem) and one industrial variant , represented by the following device trees: - shikra-cqm-som.dtsi : Retail SoM with modem - shikra-cqs-som.dtsi : Retail SoM without modem - shikra-iqs-som.dtsi : Industrial SoM without modem Signed-off-by: Komal Bajaj <[email protected]>
Add device trees for the Shikra EVK platform, which combines Shikra SoM with a common carrier board. Introduce DTS files for CQM, CQS and IQS EVK variants: - shikra-cqm-evk.dts - shikra-cqs-evk.dts - shikra-iqs-evk.dts Also add a shared include file, shikra-evk.dtsi, which contains the common daughter card nodes used across Shikra EVK variants. Signed-off-by: Komal Bajaj <[email protected]>
Add the reserved memory nodes for Shikra. Signed-off-by: Bibek Kumar Patro <[email protected]>
Add the apps and adreno smmu node as found in Shikra SoC. Signed-off-by: Bibek Kumar Patro <[email protected]>
Add qcom,shikra-apcs-hmss-global for the APCS mailbox binding. This avoids undocumented-compatible warnings from checkpatch and keeps schema constraints aligned for this target. Signed-off-by: Vishnu Santhosh <[email protected]>
Add the RPM message RAM SRAM region and APCS HMSS global mailbox controller, and wire them up to a new glink-edge node. The rpm_msg_ram node exposes the shared SRAM used for GLINK FIFOs and includes the apss_mpm sub-node for the MPM sleep counter. The `qcom,glink-rpm` transport uses: - `qcom,rpm-msg-ram` for shared GLINK FIFOs - APCS mailbox channel 0 for kick/notify This enables RPM GLINK-based inter-processor communication on Shikra. Signed-off-by: Vishnu Santhosh <[email protected]>
Add qfprom node and its properties for Shikra SoC. Signed-off-by: Komal Bajaj <[email protected]>
Move rpm_requests node to under glink-edge node. Signed-off-by: Sneh Mankad <[email protected]>
Add support for RPMCC and GCC nodes on Shikra platforms. Signed-off-by: Imran Shaik <[email protected]>
Add spmi-pmic-arb device for the SPMI PMIC arbiter found on shikra. Signed-off-by: Rakesh Kota <[email protected]>
Add the RPM SMD power domain controller node for Shikra with a complete OPP table covering all 8 voltage corners from MIN_SVS to TURBO_NO_CPR. Signed-off-by: Rakesh Kota <[email protected]>
Add RPM regulator for the Shikra Retail (CQM/CQS) SOM variants using pm4125-regulators with S1-S4 buck switchers and L1-L22 LDOs, and for the Industrial (IQS) SOM variant using pm8150-regulators with S4-S9 buck switchers and L1-L18 LDOs. Signed-off-by: Rakesh Kota <[email protected]>
Add the watchdog node for Shikra SoC. Signed-off-by: Komal Bajaj <[email protected]>
Describe the TCSR mutex hwlock controller and reference it from the SMEM node to enable proper hardware locking on Shikra. Signed-off-by: Komal Bajaj <[email protected]>
Add interconnect devices for config_noc, system_noc, mc_virt, clk_virt, mem_noc, mmnrt_virt and mmrt_virt. This will allow consumers to get their path and set bandwidth constraints on them. Signed-off-by: Raviteja Laggyshetty <[email protected]>
Add the SCM firmware node and TCSR syscon required to support download mode on Shikra. Signed-off-by: Komal Bajaj <[email protected]>
Enable console support for shikra. Signed-off-by: Xueyao An <[email protected]>
Add support for eMMC on shikra SoC and enable the required pinctrl configurations. Signed-off-by: Monish Chunara <[email protected]>
Enable eMMC for shikra CQS, CQM and IQS EVK variants. Signed-off-by: Monish Chunara <[email protected]>
Add support for SD card on shikra SoC and enable the required pinctrl configurations. Signed-off-by: Monish Chunara <[email protected]>
Add usb related changes on Shikra specifically: a) Primary controller node b) Primary high speed phy c) QMP Phy for super speed operation Enable USB controller and phys in device mode on CQS and CQM variants. Add the regulators for the phys accordingly. Signed-off-by: Krishna Kurapati <[email protected]>
Add cpufreq-hw node to support cpufreq scaling on Qualcomm Shikra SoCs. Signed-off-by: Imran Shaik <[email protected]>
Add SMP2P nodes for the cdsp, modem and lmcu subsystems to enable inter-processor signalling for remoteproc state management. Signed-off-by: Vishnu Santhosh <[email protected]>
Enable primary usb controller on IQS platform in peripheral mode. Signed-off-by: Krishna Kurapati <[email protected]>
The shikra includes one TSENS instance, with a total of 14 thermal sensors distributed across various locations on the SoC. The TSENS max/reset threshold is configured to 120°C in the hardware. Enable all TSENS instances, and define the thermal zones with a hot trip at 110°C and critical trip at 115°C. Signed-off-by: Gaurav Kohli <[email protected]>
Traditionally, firmware loading for Serial Engines (SE) in the QUP hardware of Qualcomm SoCs has been managed by TrustZone (TZ). While this approach ensures secure SE assignment and access control, it limits flexibility for developers who need to enable various protocols on different SEs. Add the firmware-name property to QUPv3 nodes in the device tree to enable firmware loading from the Linux environment. Handle SE assignments and access control permissions directly within Linux, removing the dependency on TrustZone. Signed-off-by: Xueyao An <[email protected]>
Add PMIC topic overlay changes for Shikra SOM variants (CQM, CQS, IQS): - Add pm4125 temp-alarm and VADC channel nodes - Add pm8005 temp-alarm node - Add thermal zones for PMIC and system thermistors - Add GPIO key (volume up) bindings - Add ADC thermal bridge nodes for pa/quiet/msm thermistors - Disable pm8005 regulators across SOM variants - Switch SPMI interrupt to MPM edge-triggered Signed-off-by: Rakesh Kota <[email protected]>
Add support for DISPCC and GPUCC nodes on Qualcomm Shikra platforms. Signed-off-by: Imran Shaik <[email protected]>
Add clock entries for adreno smmu node in Shikra. Signed-off-by: Bibek Kumar Patro <[email protected]>
Introduce the WiFi hardware description in shikra.dtsi, including register space, interrupts, IOMMU configuration and reserved memory. The node is kept disabled by default and is intended to be enabled by board-specific device trees. Signed-off-by: Miaoqing Pan <[email protected]>
Add device tree support for QUPv3 serial engine protocols on Shikra. Shikra has 10 QUP serial engines under a single QUP wrapper, all with support of GPI DMA engines. Signed-off-by: Xueyao An <[email protected]>
Enable USB role switching and USB-C orientation handling for the Qualcomm shikra board. Signed-off-by: Rakesh Kota <[email protected]>
Flip RPMh tags so CPU configuration paths use RPM_ACTIVE_TAG and video memory paths use RPM_ALWAYS_TAG, matching intended power management behavior. Signed-off-by: Dikshita Agarwal <[email protected]>
Add a DT node for the Last Level Cache Controller (LLCC) on the Shikra SoC. Signed-off-by: Komal Bajaj <[email protected]>
Add nodes for remoteproc PAS loader for CDSP, LPAICP, MPSS subsystem. Signed-off-by: Bibek Kumar Patro <[email protected]>
Enable CDSP, LPAICP and MPSS for Qualcomm's shikra-cqm board. Signed-off-by: Bibek Kumar Patro <[email protected]>
Enable CDSP and LPAICP for Qualcomm's shikra-cqs board. Signed-off-by: Bibek Kumar Patro <[email protected]>
Enable CDSP and LPAICP for Qualcomm's shikra-iqs board. Signed-off-by: Bibek Kumar Patro <[email protected]>
Add cooling-cells property to the CPU nodes to support cpufreq cooling devices. Signed-off-by: Aastha Pandey <[email protected]>
Update reserved memory regions for Shikra aligning with new set of no-map regions. Signed-off-by: Bibek Kumar Patro <[email protected]>
Fix compatible entries for apps_smmu and adreno_smmu nodes, add missing "qcom,adreno-smmu" compatible entry for adreno_smmu node. Signed-off-by: Bibek Kumar Patro <[email protected]>
Modify MPM pin count to incorporate all MPM interrupts that can be configured. Signed-off-by: Sneh Mankad <[email protected]>
Remove unused regulators (s1, s4, l1, l2, l11) and tighten min/max voltage ranges for remaining rails to match actual operating voltages derived from PGA report analysis. Signed-off-by: Rakesh Kota <[email protected]>
Add CX power domain support to GCC node on Shikra platform. Signed-off-by: Imran Shaik <[email protected]>
Modify compatible for Shikra mailbox APCS device and add fallback compatible string. Signed-off-by: Sneh Mankad <[email protected]>
Add DT nodes for the CoreSight debug and trace subsystem on Qualcomm Shikra SoC. Signed-off-by: Jie Gan <[email protected]>
Enable uart8 and add WCN3988 Bluetooth node with board-specific regulator supplies across CQM, CQS and IQS Shikra EVK variants. Signed-off-by: Yepuri Siddu <[email protected]>
Add the SoC-level display subsystem nodes for Shikra: MDSS wrapper, DPU display controller, DSI host controller, and 14nm DSI PHY. Shikra uses DPU 6.5 hardware (same as QCM2290), with platform-specific compatibles qcom,shikra-dpu and qcom,shikra-dsi-ctrl. The dispcc clock inputs for the DSI byte and pixel PLLs are wired from mdss_dsi0_phy. Signed-off-by: Mahadevan P <[email protected]>
Enable the Shikra MDSS display subsystem on the CQM EVK board and add the DLC0697 panel node. Pin pm4125_l5 to 1.232V with regulator-allow-set-load for DSI PHY PLL stability. Signed-off-by: Mahadevan P <[email protected]>
Add qcrypto and cryptobam support for shikra target. Link: https://lore.kernel.org/lkml/[email protected]/ Signed-off-by: Kuldeep Singh <[email protected]>
Add True Random Number Generator(TRNG) node for shikra. Link: https://lore.kernel.org/lkml/[email protected]/ Signed-off-by: Kuldeep Singh <[email protected]>
Add UFS inline crypto engine(ICE) support for shikra. Link: https://lore.kernel.org/lkml/[email protected] Signed-off-by: Kuldeep Singh <[email protected]>
Add pm4125_s1 regulator node at fixed 1.396V to both shikra-cqm-som and shikra-cqs-som. This rail is used by the audio subsystem. Signed-off-by: Rakesh Kota <[email protected]>
Add a separate fixed dummy regulator for Bluetooth. Signed-off-by: Yepuri Siddu <[email protected]>
Enable the DLC0697 MIPI DSI display panel on the Shikra CQS EVK. Signed-off-by: Mahadevan P <[email protected]>
If the remoteproc dump_conf is not configured, trigger a SoC reset via panic() on both watchdog and fatal error interrupts before reporting the crash. This ensures the system resets cleanly when coredump collection is not enabled. Signed-off-by: Anurag Pateriya <[email protected]>
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If the remoteproc dump_conf is not configured, trigger a SoC reset via panic() on both watchdog and fatal error interrupts before reporting the crash. This ensures the system resets cleanly when coredump collection is not enabled.