hw/riscv: add SpacemiT K3 Pico-ITX machine#9
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SpacemiT K3 uses eight X100 application harts implementing RVA23S64. Add a spacemit-x100 vendor CPU with RVH, a 256-bit VLEN, Sv39, and AIA support so board models can select the hardware CPU directly. Signed-off-by: Chao Liu <[email protected]>
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Model the Linux-visible X100 subset with two four-hart RVA23S64 clusters, fixed 2 GiB RAM, a 24 MHz ACLINT, M/S APLIC and IMSIC controllers, and UART0. Use the dedicated spacemit-x100 CPU type and keep H disabled for this Linux-first subset because the VS interrupt path is not modeled. Support direct Linux boot through generic OpenSBI and an external device tree. Keep the A100 harts and vendor firmware path outside the current machine contract. Signed-off-by: Chao Liu <[email protected]>
Cover the fixed spacemit-x100 CPU type and topology, 256-bit VLEN, firmware and DRAM windows, 24 MHz timer and Sstc behavior, per-hart M/S IMSIC routing, and the UART0 interrupt path through the M/S APLIC hierarchy. Signed-off-by: Chao Liu <[email protected]>
Boot pinned SDK v1.0.2 artifacts through generic OpenSBI and verify the Linux-visible platform contract, all eight X100 harts, interrupt controllers, UART, and the initramfs completion marker. Use content-addressed assets from the public K3 QEMU image release. Signed-off-by: Chao Liu <[email protected]>
SDHCI currently clears Transfer Mode DMA unless the controller advertises SDMA. This prevents ADMA-only controllers from using DMA even when ADMA1 or ADMA2 is available. Keep DMA enabled when any implemented DMA engine is advertised. Check the SDMA capability in the transfer dispatcher as well, matching the existing ADMA checks and preventing an ADMA-only controller from selecting SDMA. Signed-off-by: Chao Liu <[email protected]>
K3 U-Boot reads the boot source from the chip interface unit and programs the application power management unit while probing SDHCI0. Unmapped accesses stop the boot path before storage initialization. Add narrow CIU and APMU models. Report SD as the boot source and implement the SDH0 reset, gate, mux, divider, and self-clearing frequency-change fields. Log accesses outside the modeled firmware contract instead of providing a catch-all register bank. Signed-off-by: Chao Liu <[email protected]>
K3 SDHCI0 follows the standard version 3 register layout but adds a small vendor register bank for card-mode and transmit-clock controls. The generic SDHCI device cannot expose those registers or the K3 capability set directly. Add a wrapper which embeds the generic controller, advertises the 3.3 V SD High Speed and ADMA2 features used by K3 U-Boot, and implements only the vendor fields touched on that boot path. Pass the SD bus and interrupt through so the board can attach storage and route IRQ 99 separately. Signed-off-by: Chao Liu <[email protected]>
K3 U-Boot proper expects writable on-chip SRAM, a small handoff scratch window, the SDHCI0 clock and boot controls, and an SD card on the first host. The machine currently exposes only the reset-vector page and standard RISC-V platform devices, so firmware cannot reach storage. Expand the SRAM mapping, add the reset-cleared scratch window, map the K3 control and SDHCI devices, route SDHCI0 interrupt 99 to the APLIC, and attach legacy SD unit zero. Keep BootROM, SPL, and DDR training outside the model; generic OpenSBI continues to load either Linux directly or U-Boot proper. Signed-off-by: Chao Liu <[email protected]>
The K3 machine now exposes the storage devices required by U-Boot, but the existing tests cover only the original direct-Linux platform subset. A firmware test alone would not localize regressions in reset state, DMA, or AIA routing. Extend the machine qtest for the SRAM and boot-control registers, then attach a deterministic temporary SD image and read its first sector through a 64-bit ADMA2 descriptor above 4 GiB. Verify the data and route SDHCI0 source 99 through the delegated APLIC to an S-mode IMSIC. Signed-off-by: Chao Liu <[email protected]>
Signed-off-by: Chao Liu <[email protected]>
Describe the Linux-first X100 subset, fixed topology and memory map, supported interrupt and serial devices, direct OpenSBI boot command, and current model limitations. Add the machine and its tests to MAINTAINERS. Signed-off-by: Chao Liu <[email protected]>
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Cross-build jobs validate compilation and installation across container toolchains. Building the same Sphinx documentation in every container adds no cross-target coverage and can fail nondeterministically when Sphinx parallel workers exit with EOFError. Disable documentation through EXTRA_CONFIGURE_OPTS for the cross-build matrix. Native jobs continue to build the documentation. Signed-off-by: Chao Liu <[email protected]>
page_check_range() may race with pageflags_set_clear() when the latter mutates interval-tree node bounds after a reader has found the node. This can make a valid guest range appear inaccessible and fail vma-pthread with Bad address. Keep node bounds immutable by replacing changed nodes and freeing the old ones through RCU. Guard lockless readers so they cannot use freed nodes. This is a downstream backport of upstream commit e03b7da. Signed-off-by: Chao Liu <[email protected]>
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Summary
develat90ff589972, with no upstream synchronization merge in the PRspacemit-x100CPU type as the first K3 patchk3-pico-itxmachine with eight X100 harts, fixed 2 GiB RAM, ACLINT, APLIC/IMSIC, and UART0README.mdmachine tableBoot paths
The direct path is:
QEMU reset vector -> OpenSBI fw_dynamic.bin -> Linux Image -> initramfsThe firmware path is:
QEMU reset vector -> OpenSBI fw_dynamic.bin -> U-Boot proper -> SD -> LinuxBootROM, bootinfo parsing, SPL, LPDDR training, and HS boot are intentionally out of scope. QEMU supplies initialized RAM and starts generic OpenSBI directly.
Pinned functional-test assets are published at:
https://github.com/zevorn/spacemit-k3-qemu-images/releases/tag/sdk-v1.0.2-qemu2
Review and CI fixes
fdt_node_check_compatible()so compatible string lists are acceptedv=falsedevelAPIEXTRA_CONFIGURE_OPTS=--disable-docs; native CI jobs continue to build documentatione03b7dac65d9so lockless PageFlags readers cannot race with mutable interval-tree bounds; this fixes the aarch64-hostvma-pthreadBad address failure without skipping the testValidation
-Werrorbuild with--disable-docs --disable-gio-Werror(4288/4288 targets)qemu:qtest-riscv64/spacemit-k3-test— 10 subtests passedqemu:func-riscv64-spacemit_k3with the thorough setup — 2 subtests passede03b7dac65d9git diff --check origin/devel..HEADSigned-off-by: Chao Liu <[email protected]>