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downstream: rebase hardware models onto master#12

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codex/rebase-devel-onto-master-20260715
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downstream: rebase hardware models onto master#12
zevorn wants to merge 140 commits into
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codex/rebase-devel-onto-master-20260715

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@zevorn

@zevorn zevorn commented Jul 15, 2026

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Summary

  • Rebase the downstream hardware-modeling series from devel onto the current
    downstream master, retaining the master implementation wherever the two
    branches overlap.
  • Preserve the downstream AX650X Pyramid, CanMV K230, SpacemiT K3, Milk-V Duo,
    Phytium Pi, RK3588, S32K5, and RISC-V server-reference machine work as an
    atomic, non-merge series.
  • Keep complex AX650X peripherals, including the DesignWare MAC path, in
    dedicated device source files instead of growing the board file.
  • Add the documented AX650X Ubuntu quick-boot flow and functional test using
    public remote release assets, so CI does not depend on developer-local image
    paths.

Integration decisions

  • Git skipped 70 downstream patches that are already represented on master.
  • Current QEMU API adaptations were folded into the feature commits that own
    the affected devices; no aggregate fixup or cover-letter commit remains.
  • The K230 QEMU finisher was dropped because its 0x00100000 MMIO mapping
    overlaps guest DDR and intercepted normal Linux memory traffic. Both direct
    boot and U-Boot/OpenSBI/Linux boot pass with the existing K230 PMU poweroff
    model.
  • The master RISC-V TCG interrupt gate remains intact for normal execution; a
    focused qtest exception preserves device interrupt observability when TCG is
    not running.
  • The upstream-oriented lockdown workflow remains disabled for this downstream
    repository because it would automatically close downstream integration PRs.

Validation

  • Full isolated build: aarch64-softmmu, arm-softmmu, and
    riscv64-softmmu.
  • Full 140-commit checkpatch pass: zero errors.
  • Focused qtests: 10 binaries, 136 subtests, all passed.
  • Functional boots: K230 direct boot, K230 U-Boot/OpenSBI/Linux, AX650X Ubuntu
    remote-asset quick boot, and two SpacemiT K3 remote-asset paths, all passed.
  • Sphinx manual and man-page generation passed.
  • git diff --check, DCO, attribution, and final-history audits passed.

zevorn added 30 commits July 15, 2026 22:01
@zevorn
target/riscv: add K230 C908 runtime quirks
9eb748e 
Signed-off-by: Chao Liu <[email protected]>
@zevorn
hw/dma: add k230 DMA controllers
b2478d0 
Add K230 GSDMA and PDMA sysbus devices used by the K230 SDK boot flow.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
hw/sd: add k230 SDHCI controller
3f0aff6 
Add the K230 DWC MSHC wrapper around the generic SDHCI model, including the vendor register window needed by SDK software.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
hw/misc: add k230 support register blocks
9d77101 
Add K230 MMIO models for SDK-visible support blocks, including UGZIP, hardlock, GPIO, ADC, PWM, timers, thermal sensor, and high-speed system config registers.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
hw/riscv: wire up k230 SDK boot devices
5f627c9 
Instantiate the K230 SDK-visible support devices, attach legacy SD drives to the machine SD slots, and select the required device models from the K230 machine.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
docs/system/riscv: update k230 U-Boot boot docs
776edbd 
Document SD card image boot through SDK U-Boot now that the K230 machine can model the SDK storage and decompression path.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
hw/misc: add K230 sysctl blocks
82ee715 
Model the K230 boot and power sysctl register windows used by the SDK firmware during Linux boot. The boot block reports locked PLLs, while the power block tracks simple domain on/off status and AI repair completion.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
hw/ssi: add K230 SPI controller
7ef5822 
Add a small DesignWare SSI-compatible K230 SPI model for the SDK boot flow. It provides MMIO register state, FIFO accesses, flash command forwarding through an SSI bus, and the simple IDMA path used by the firmware.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
hw/usb: add RTL8152 USB Ethernet device
aa13783 
Add a Realtek RTL8152 USB Ethernet model backed by QEMU NIC queues. The device implements the vendor register accesses, link status interrupt endpoint, RX/TX descriptors, and checksum fixups needed by the Linux r8152 driver.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
hw/riscv: wire K230 sysctl, SPI and USB devices
3bf31bf 
Instantiate the K230 sysctl, SPI and DWC2 USB controllers at the SoC addresses used by the SDK. Attach an RTL8152 USB NIC to usb1 and make it the default NIC model so the emulated board matches the CANMV hardware path instead of using virtio networking.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
MAINTAINERS: add K230 SPI and RTL8152 entries
5078265 
List the K230 SPI model with the K230 machine files and add a maintained entry for the RTL8152 USB Ethernet device.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
hw/i2c: add K230 I2C controller
83e7e20 
Add a small DesignWare I2C compatible controller for the K230 SoC. The model keeps the SDK-visible register state and forwards simple transfers through a QEMU I2C bus so board code can replace the placeholder MMIO windows.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
hw/misc: add K230 register block models
88e859a 
Add the K230 IOMUX window, a reusable scratch register block, and the security window pieces used by the SDK boot flow. The security model returns random data from the TRNG register and keeps OTP reads harmless while the remaining register-only blocks preserve guest writes.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
hw/gpio: add K230 interrupt support
dce2759 
Model the K230 GPIO interrupt enable, mask, type, polarity and both-edge registers and expose one sysbus IRQ per GPIO line. This lets board code route GPIO bank interrupts through the PLIC instead of treating the block as a register-only device.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
hw/rtc: add K230 RTC model
4195215 
Add a K230 RTC model for the MMIO layout documented by the K230 TRM and used by the SDK RT-Smart driver. The device exposes date, time, alarm, count and interrupt-control registers and keeps the guest-visible clock advancing from QEMU's rtc_clock.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
hw/riscv: wire more K230 peripherals
23dfeab 
Instantiate the K230 IOMUX, I2C, RTC, security, QSPI and scratch register blocks at the addresses used by the SDK. Route GPIO bank lines and the RTC PMU interrupt through the PLIC, attach the MTD flash image to the SPI flash model, and expose the flash XIP window from that backing image.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
MAINTAINERS: add K230 I2C and RTC entries
b627d37 
List the K230 I2C and RTC model files with the rest of the K230 machine sources so get_maintainer covers the newly added peripheral models.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
hw/misc: model K230 security engine side effects
ba9ecd0 
The SDK security drivers expect DMA, hash, key wrap, key allocator and RSA start bits to leave the engine in a completed state.  Keep the model lightweight but add those completion side effects so Linux can make progress through the hardware probes and self-tests.

Use a bounded DMA memory copy for descriptor starts and report empty digest data for the unsupported crypto transforms.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
hw/misc: add K230 IPCM interrupt state
84aea58 
The hardlock block also exposes IPCM interrupt registers used by the SDK mailbox path.  Add the interrupt enable, set, clear and status behavior and expose four IRQ lines so the board can route DSP-to-CPU events.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
hw/riscv: wire K230 IPCM interrupts
c1e2488 
Route the hardlock IPCM interrupt outputs to the C908 PLIC lines used by the SDK mailbox driver.  This lets the board model deliver DSP-to-CPU mailbox events instead of only storing the IPCM register state.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
hw/misc: add K230 PMU poweroff model
9e5eece 
The SDK Linux poweroff path programs the PMU shutdown sequence instead of touching QEMU-specific devices.  Replace the generic register window with a small PMU model that preserves scratch register behavior and recognizes the normal powerdown sequence so guest poweroff exits QEMU cleanly.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
hw/display: add K230 VO and DSI models
d2194dc 
Add the K230 video output and MIPI DSI register blocks and wire them into the board in place of the previous unimplemented regions.  The VO model exposes a QEMU graphical console, handles OSD framebuffer formats used by the SDK, pulses the display interrupt and keeps a fbdev compatibility scanout path for the current non-Tee LCD image.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
MAINTAINERS: add K230 display entries
73da10c 
List the K230 display model files with the rest of the K230 machine sources so get_maintainer covers the newly added VO and DSI implementation.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
hw/intc: add K230 S-mode CLINT
5ffc6cd 
Add the K230 T-Head C908 S-mode CLINT window used for SSIP and STIMECMP access from RT-Smart.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
hw/misc: add K230 non-AI 2D model
93513bc 
Model the K230 non-AI 2D copy engine registers used by the RT-Smart media path, including planar and packed buffer copies and completion IRQ state.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
hw/misc: add K230 ISP model
f4d5cfd 
Add a lightweight K230 ISP register model for the frame-start and MCM interrupt/status paths exercised by the RT-Smart media stack.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
hw/misc: add K230 dewarp model
dd11eae 
Add the K230 dewarp/FE/VSE register and interrupt behavior needed by the RT-Smart media pipeline.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
hw/misc: add K230 RX CSI model
5bb6a5e 
Add the K230 RX CSI register behavior used by sensor bring-up, including ready PHY status and display-frame configuration registers.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
hw/riscv: wire expanded K230 SoC devices
4a03c8c 
Instantiate the split C908/C908V CPU domains and connect the K230 CLINT, media, camera, KPU completion, and interrupt routing models into the machine.

Register the new K230 device selections and extend the maintainer file patterns for the added local models.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
tests/qtest: add K230 system controller coverage
1830632 
Add a focused K230 qtest covering the dual-core topology, S-mode CLINT window, OV5647 probe path, and media peripheral completion behavior.

The KPU case constrains fake completion to pages referenced by the command buffer inside the modeled output window.

Signed-off-by: Chao Liu <[email protected]>
zevorn added 27 commits July 15, 2026 22:54
@zevorn
target/riscv: add SpacemiT X100 CPU type
5931efe 
SpacemiT K3 uses eight X100 application harts implementing RVA23S64.
Add a spacemit-x100 vendor CPU with RVH, a 256-bit VLEN, Sv39, and AIA
support so board models can select the hardware CPU directly.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
hw/riscv: add SpacemiT K3 Pico-ITX machine
79aab7a 
Model the Linux-visible X100 subset with two four-hart RVA23S64
clusters, fixed 2 GiB RAM, a 24 MHz ACLINT, M/S APLIC and IMSIC
controllers, and UART0.

Use the dedicated spacemit-x100 CPU type and keep H disabled for this
Linux-first subset because the VS interrupt path is not modeled.

Support direct Linux boot through generic OpenSBI and an external device
tree. Keep the A100 harts and vendor firmware path outside the current
machine contract.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
tests/qtest: add SpacemiT K3 machine tests
b8f0c19 
Cover the fixed spacemit-x100 CPU type and topology, 256-bit VLEN,
firmware and DRAM windows, 24 MHz timer and Sstc behavior, per-hart M/S
IMSIC routing, and the UART0 interrupt path through the M/S APLIC
hierarchy.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
tests/functional/riscv64: add SpacemiT K3 Linux boot test
ecf3571 
Boot pinned SDK v1.0.2 artifacts through generic OpenSBI and verify
the Linux-visible platform contract, all eight X100 harts, interrupt
controllers, UART, and the initramfs completion marker.

Use content-addressed assets from the public K3 QEMU image release.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
hw/sd: allow ADMA without SDMA capability
6d8179a 
SDHCI currently clears Transfer Mode DMA unless the controller advertises
SDMA.  This prevents ADMA-only controllers from using DMA even when ADMA1
or ADMA2 is available.

Keep DMA enabled when any implemented DMA engine is advertised.  Check the
SDMA capability in the transfer dispatcher as well, matching the existing
ADMA checks and preventing an ADMA-only controller from selecting SDMA.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
hw/misc: add SpacemiT K3 clock and boot controls
de6250e 
K3 U-Boot reads the boot source from the chip interface unit and programs
the application power management unit while probing SDHCI0.  Unmapped
accesses stop the boot path before storage initialization.

Add narrow CIU and APMU models.  Report SD as the boot source and implement
the SDH0 reset, gate, mux, divider, and self-clearing frequency-change
fields.  Log accesses outside the modeled firmware contract instead of
providing a catch-all register bank.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
hw/sd: add SpacemiT K3 SDHCI controller
7922f12 
K3 SDHCI0 follows the standard version 3 register layout but adds a small
vendor register bank for card-mode and transmit-clock controls.  The generic
SDHCI device cannot expose those registers or the K3 capability set directly.

Add a wrapper which embeds the generic controller, advertises the 3.3 V SD
High Speed and ADMA2 features used by K3 U-Boot, and implements only the
vendor fields touched on that boot path.  Pass the SD bus and interrupt
through so the board can attach storage and route IRQ 99 separately.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
hw/riscv: add SD card support to SpacemiT K3
05b15ea 
K3 U-Boot proper expects writable on-chip SRAM, a small handoff scratch
window, the SDHCI0 clock and boot controls, and an SD card on the first host.
The machine currently exposes only the reset-vector page and standard RISC-V
platform devices, so firmware cannot reach storage.

Expand the SRAM mapping, add the reset-cleared scratch window, map the K3
control and SDHCI devices, route SDHCI0 interrupt 99 to the APLIC, and attach
legacy SD unit zero.  Keep BootROM, SPL, and DDR training outside the model;
generic OpenSBI continues to load either Linux directly or U-Boot proper.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
tests/qtest: cover SpacemiT K3 SD boot hardware
e34de52 
The K3 machine now exposes the storage devices required by U-Boot, but the
existing tests cover only the original direct-Linux platform subset.  A
firmware test alone would not localize regressions in reset state, DMA, or AIA
routing.

Extend the machine qtest for the SRAM and boot-control registers, then attach
a deterministic temporary SD image and read its first sector through a
64-bit ADMA2 descriptor above 4 GiB.  Verify the data and route SDHCI0 source
99 through the delegated APLIC to an S-mode IMSIC.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
tests/functional/riscv64: boot SpacemiT K3 Linux from U-Boot
5d49f32 
Signed-off-by: Chao Liu <[email protected]>
@zevorn
docs/system/riscv: document SpacemiT K3 Pico-ITX machine
184ad39 
Describe the Linux-first X100 subset, fixed topology and memory map,
supported interrupt and serial devices, direct OpenSBI boot command, and
current model limitations.

Add the machine and its tests to MAINTAINERS.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
ci: disable documentation in cross builds
9f2a387 
Cross-build jobs validate compilation and installation across container
toolchains. Building the same Sphinx documentation in every container adds
no cross-target coverage and can fail nondeterministically when Sphinx
parallel workers exit with EOFError.

Disable documentation through EXTRA_CONFIGURE_OPTS for the cross-build
matrix. Native jobs continue to build the documentation.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
docs/system/riscv: update SpacemiT K3 boot details
506ce08 
Signed-off-by: Chao Liu <[email protected]>
@zevorn
hw/arm: Add AX650X Pyramid machine skeleton
3508bb9 
Model the eight Cortex-A55 CPUs, high 2 GiB RAM window, GIC-400, architectural timers, PMU interrupts, PSCI and the boot UART. Generate a minimal device tree for direct Linux kernel boot.

Add qtests for the CPU affinities, RAM window, GICv2 topology, virtualization interface, UART interrupt routing and reset behavior.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
hw/sd: Add AX650X SDHCI controller
42e310b 
Model the AX650X SDHCI wrapper around QEMU's generic controller. Add the vendor pointer, PHY/DLL register bank, eMMC reset control, and the embedded-card capability used by the vendor Linux driver.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
hw/arm: Wire AX650X Pyramid eMMC
6842dcf 
Instantiate the AX650X SDHCI wrapper at the hardware address, connect SPI 93, and attach an eMMC backend supplied through if=sd. Describe the controller, clocks, capabilities, and PHY tuning properties in the generated device tree.

Exercise the vendor, PHY, DLL and eMMC control registers, reset state, SDHCI capabilities, interrupt routing, and programmed-I/O block transfers with qtest.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
hw/arm: Model AX650X UART extension window
c42f2c0 
Add the AX650X UART extension register window and verify its reset, read and write behavior with qtest.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
hw/sd: Advertise AX650X 64-bit ADMA support
58c83bf 
Expose the AX650X SDHCI 64-bit ADMA capability and verify the capability bit with qtest.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
hw/sd: Implement SDHCI Auto CMD23
6b20a4d 
Implement SDHCI Auto CMD23 handling and exercise the AX650X command path with qtest.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
docs/system/arm: Document AX650X Pyramid machine
88030f5 
Signed-off-by: Chao Liu <[email protected]>
@zevorn
hw/gpio: add DesignWare APB GPIO model
140821d 
Signed-off-by: Chao Liu <[email protected]>
@zevorn
hw/misc: add AX650X Ethernet support blocks
da12cc9 
Signed-off-by: Chao Liu <[email protected]>
@zevorn
hw/net: refine DWMAC4 DMA and PHY behavior
383346d 
Signed-off-by: Chao Liu <[email protected]>
@zevorn
hw/arm: integrate AX650X DWMAC topology
2d338c1 
Instantiate the AX650X Ethernet topology and verify the glue, GPIO, hwspinlock, MDIO, PHY, DMA and interrupt behavior with qtest.

Signed-off-by: Chao Liu <[email protected]>
@zevorn
tests/functional: add AX650X Ubuntu quick boot
80b54e1 
Signed-off-by: Chao Liu <[email protected]>
@zevorn
docs/system/arm: document AX650X Ubuntu boot
963783c 
Signed-off-by: Chao Liu <[email protected]>
@zevorn
target/riscv: preserve interrupt state under qtest
c329391 
Keep the architectural interrupt-pending state in sync when qtests drive RISC-V interrupt inputs.  This matches the TCG path and lets qtests observe timer and external interrupt transitions without a running vCPU.

Signed-off-by: Chao Liu <[email protected]>
@zevorn

zevorn commented Jul 15, 2026

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Closed because this downstream integration was published directly to the devel branch.

@zevorn zevorn closed this Jul 15, 2026
@zevorn
zevorn deleted the codex/rebase-devel-onto-master-20260715 branch July 15, 2026 15:02
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4 participants

@zevorn @visitorckw @danielhb @wufei-sanechips