hw/arm: add AX650X Pyramid Linux boot model#11
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Model the eight Cortex-A55 CPUs, high 2 GiB RAM window, GIC-400, architectural timers, PMU interrupts, PSCI and the boot UART. Generate a minimal device tree for direct Linux kernel boot. Add qtests for the CPU affinities, RAM window, GICv2 topology, virtualization interface, UART interrupt routing and reset behavior. Signed-off-by: Chao Liu <[email protected]>
Model the AX650X SDHCI wrapper around QEMU's generic controller. Add the vendor pointer, PHY/DLL register bank, eMMC reset control, and the embedded-card capability used by the vendor Linux driver. Signed-off-by: Chao Liu <[email protected]>
Instantiate the AX650X SDHCI wrapper at the hardware address, connect SPI 93, and attach an eMMC backend supplied through if=sd. Describe the controller, clocks, capabilities, and PHY tuning properties in the generated device tree. Exercise the vendor, PHY, DLL and eMMC control registers, reset state, SDHCI capabilities, interrupt routing, and programmed-I/O block transfers with qtest. Signed-off-by: Chao Liu <[email protected]>
Add the AX650X UART extension register window and verify its reset, read and write behavior with qtest. Signed-off-by: Chao Liu <[email protected]>
Expose the AX650X SDHCI 64-bit ADMA capability and verify the capability bit with qtest. Signed-off-by: Chao Liu <[email protected]>
Implement SDHCI Auto CMD23 handling and exercise the AX650X command path with qtest. Signed-off-by: Chao Liu <[email protected]>
Signed-off-by: Chao Liu <[email protected]>
Signed-off-by: Chao Liu <[email protected]>
Signed-off-by: Chao Liu <[email protected]>
Signed-off-by: Chao Liu <[email protected]>
Instantiate the AX650X Ethernet topology and verify the glue, GPIO, hwspinlock, MDIO, PHY, DMA and interrupt behavior with qtest. Signed-off-by: Chao Liu <[email protected]>
Signed-off-by: Chao Liu <[email protected]>
Signed-off-by: Chao Liu <[email protected]>
Signed-off-by: Chao Liu <[email protected]>
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Summary
ax650x-pyramidArm machine with eight Cortex-A55 CPUs, GICv2,PSCI, UART, AX650X SDHCI/eMMC, and direct Linux boot support
clock/reset glue, hardware spinlock, MDIO/PHY, DMA, IRQ, and FDT integration
devices, limitations, and test commands
Why
The M5Stack AI Pyramid uses an AXERA AX650X runtime platform that is not
represented by an existing QEMU Arm machine. This series provides the
hardware subset needed to run the AXERA Linux 5.15.73 kernel and boot Ubuntu
22.04 from eMMC partition 12 under TCG.
Complex peripherals are kept outside the board file: reusable GPIO, glue,
spinlock, DWMAC, and SDHCI behavior live in their respective subsystems, while
hw/arm/ax650x-dwmac.cowns only board topology and generated FDT nodes.Functional assets
The functional test downloads its inputs from the immutable
ax650x-ubuntu-22.04-qemu1release and verifies both SHA-256 digests before boot:
9e3dc56e13cb5e786864d3456ceecfe7560d11fd25e9688531f86c0748be9bf8e362cff67d7358bc434394649f91d0b2424156eb9cd3b518438cf32fe3b9800cThe qcow2 is byte-equivalent to the current post-Fastfetch sparse raw image,
retains its 31,289,507,840-byte virtual layout, and is always attached with
snapshot=on.Validation
ax650x-pyramid-testbuild: PASSattribution
The functional boot reaches both DWMAC probes, all twelve eMMC partitions,
the p12 ext4 root mount, Ubuntu 22.04.5 readiness, eight online CPUs, and the
serial login prompt.
Limitations
This supports QEMU direct kernel boot. BootROM, SPL, U-Boot, TF-A, OP-TEE,
NPU, VDSP, media, display, USB, PCIe, SATA, and complete power-management
behavior remain outside this series.