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ombhilare999/README.md

Omkar Bhilare

(Digital Design and Verification Enthusiast)

I am a PhD student at the University of Toronto, working with Professor Jason Anderson. My research centers on the architecture of Coarse-Grained Reconfigurable Arrays (CGRAs) — a class of reconfigurable architectures capable of delivering near-ASIC performance and energy efficiency while retaining runtime programmability. I work on designing and exploring CGRA architectures, and also develop CAD mapping algorithms to efficiently execute applications on these devices. I also completed a research internship at RIKEN Center for Computational Science (R-CCS) with Dr. Kentaro Sano.

Before starting my PhD, I worked as a Silicon Design Engineer at AMD in India. During my undergraduate studies in Electronics, I interned with Prof. Paolo Ienne at EPFL on the Dynamatic project, with Prof. Kamakoti at IIT Madras on the Shakti processor project, and participated in Google Summer of Code with BeagleBoard.org for the BeagleWire project.

I am always open to research collaborations and opportunities in Computer Architecture, Reconfigurable Computing, and RTL Design & Verification. Feel free to reach out if you'd like to discuss ideas or any of my previous work.

Pinned Loading

  1. BeagleWire BeagleWire Public

    Forked from BeagleWire/BeagleWire

    This repository contains software for BeagleWire. Docs of BeagleWire: https://beaglewire.github.io/

    Verilog 1

  2. SRA-VJTI/sra-board-hardware-design SRA-VJTI/sra-board-hardware-design Public

    ESP32-based Development Board for Robotics and Embedded Applications

    HTML 79 27

  3. riscv-core riscv-core Public

    A customized RISCV core made using verilog

    Verilog 18 3

  4. 8-bit-computer 8-bit-computer Public

    8 bit computer using sap logic

    Python 6

  5. vga-interface-with-TANG-PRIMER-FPGA vga-interface-with-TANG-PRIMER-FPGA Public

    Interfacing Tang primer with VGA display.

    Verilog 8

  6. 8-Bit-ALU-implementation-on-CYCLONE-2 8-Bit-ALU-implementation-on-CYCLONE-2 Public

    Verilog code for 8 Bit ALU and implemented on Intel's Cyclone II

    Verilog 1