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[HLSL] Add WavePrefixCountBits tests (#686)
This PR adds the WavePrefixCountBits tests, using 32 64 and 128-sized waves. Fixes #687
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‎test/WaveOps/WavePrefixCountBits.Wave128.test‎

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#--- source.hlsl
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RWStructuredBuffer<uint> Out1 : register(u1);
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RWStructuredBuffer<uint> Out2 : register(u2);
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[WaveSize(128)]
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[numthreads(128, 1, 1)]
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void main(uint3 tid : SV_GroupThreadID) {
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// this should be an ascending sequence of numbers
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Out1[tid.x] = WavePrefixCountBits(true);
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// this should look more like 0, 1, 1, 2, 2, 3, 3, etc.
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Out2[tid.x] = WavePrefixCountBits(tid.x % 2 == 0);
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}
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//--- pipeline.yaml
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---
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Shaders:
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- Stage: Compute
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Entry: main
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DispatchSize: [1, 1, 1]
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Buffers:
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- Name: Out1
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Format: UInt32
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Stride: 4
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FillSize: 512
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- Name: ExpectedOut1
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Format: UInt32
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Stride: 4
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Data: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
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16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
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32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
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48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
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64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
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80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95,
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96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111,
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112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127]
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- Name: Out2
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Format: UInt32
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Stride: 4
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FillSize: 512
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- Name: ExpectedOut2
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Format: UInt32
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Stride: 4
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Data: [0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8,
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9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 16, 16,
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17, 17, 18, 18, 19, 19, 20, 20, 21, 21, 22, 22, 23, 23, 24, 24,
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25, 25, 26, 26, 27, 27, 28, 28, 29, 29, 30, 30, 31, 31, 32, 32,
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33, 33, 34, 34, 35, 35, 36, 36, 37, 37, 38, 38, 39, 39, 40, 40,
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41, 41, 42, 42, 43, 43, 44, 44, 45, 45, 46, 46, 47, 47, 48, 48,
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49, 49, 50, 50, 51, 51, 52, 52, 53, 53, 54, 54, 55, 55, 56, 56,
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57, 57, 58, 58, 59, 59, 60, 60, 61, 61, 62, 62, 63, 63, 64]
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Results:
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- Result: Test1
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Rule: BufferExact
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Actual: Out1
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Expected: ExpectedOut1
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- Result: Test2
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Rule: BufferExact
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Actual: Out2
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Expected: ExpectedOut2
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DescriptorSets:
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- Resources:
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- Name: Out1
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Kind: RWStructuredBuffer
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DirectXBinding:
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Register: 1
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Space: 0
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VulkanBinding:
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Binding: 2
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- Name: Out2
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Kind: RWStructuredBuffer
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DirectXBinding:
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Register: 2
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Space: 0
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VulkanBinding:
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Binding: 2
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...
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#--- end
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# REQUIRES: WaveSize_128
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# RUN: split-file %s %t
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# RUN: %dxc_target -T cs_6_6 -Fo %t.o %t/source.hlsl
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# RUN: %offloader %t/pipeline.yaml %t.o

‎test/WaveOps/WavePrefixCountBits.Wave32.test‎

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#--- source.hlsl
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RWStructuredBuffer<uint> Out1 : register(u1);
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RWStructuredBuffer<uint> Out2 : register(u2);
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[WaveSize(32)]
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[numthreads(32, 1, 1)]
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void main(uint3 tid : SV_GroupThreadID) {
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// this should be an ascending sequence of numbers
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Out1[tid.x] = WavePrefixCountBits(true);
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// this should look more like 0, 1, 1, 2, 2, 3, 3, etc.
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Out2[tid.x] = WavePrefixCountBits(tid.x % 2 == 0);
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}
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//--- pipeline.yaml
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---
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Shaders:
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- Stage: Compute
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Entry: main
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DispatchSize: [1, 1, 1]
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Buffers:
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- Name: Out1
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Format: UInt32
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Stride: 4
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FillSize: 128
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- Name: ExpectedOut1
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Format: UInt32
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Stride: 4
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Data: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
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17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
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- Name: Out2
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Format: UInt32
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Stride: 4
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FillSize: 128
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- Name: ExpectedOut2
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Format: UInt32
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Stride: 4
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Data: [0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8,
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9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 16]
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Results:
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- Result: Test1
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Rule: BufferExact
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Actual: Out1
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Expected: ExpectedOut1
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- Result: Test2
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Rule: BufferExact
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Actual: Out2
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Expected: ExpectedOut2
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DescriptorSets:
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- Resources:
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- Name: Out1
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Kind: RWStructuredBuffer
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DirectXBinding:
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Register: 1
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Space: 0
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VulkanBinding:
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Binding: 2
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- Name: Out2
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Kind: RWStructuredBuffer
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DirectXBinding:
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Register: 2
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Space: 0
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VulkanBinding:
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Binding: 2
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...
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#--- end
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# REQUIRES: WaveSize_32
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# RUN: split-file %s %t
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# RUN: %dxc_target -T cs_6_6 -Fo %t.o %t/source.hlsl
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# RUN: %offloader %t/pipeline.yaml %t.o

‎test/WaveOps/WavePrefixCountBits.Wave64.test‎

Lines changed: 78 additions & 0 deletions
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#--- source.hlsl
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RWStructuredBuffer<uint> Out1 : register(u1);
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RWStructuredBuffer<uint> Out2 : register(u2);
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[WaveSize(64)]
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[numthreads(64, 1, 1)]
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void main(uint3 tid : SV_GroupThreadID) {
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// this should be an ascending sequence of numbers
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Out1[tid.x] = WavePrefixCountBits(true);
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// this should look more like 0, 1, 1, 2, 2, 3, 3, etc.
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Out2[tid.x] = WavePrefixCountBits(tid.x % 2 == 0);
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}
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//--- pipeline.yaml
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---
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Shaders:
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- Stage: Compute
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Entry: main
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DispatchSize: [1, 1, 1]
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Buffers:
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- Name: Out1
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Format: UInt32
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Stride: 4
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FillSize: 256
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- Name: ExpectedOut1
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Format: UInt32
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Stride: 4
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Data: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
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17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
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32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
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48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63]
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- Name: Out2
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Format: UInt32
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Stride: 4
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FillSize: 256
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- Name: ExpectedOut2
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Format: UInt32
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Stride: 4
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Data: [0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8,
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9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 16,
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16, 17, 17, 18, 18, 19, 19, 20, 20, 21, 21, 22, 22, 23, 23, 24,
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24, 25, 25, 26, 26, 27, 27, 28, 28, 29, 29, 30, 30, 31, 31, 32]
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Results:
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- Result: Test1
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Rule: BufferExact
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Actual: Out1
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Expected: ExpectedOut1
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- Result: Test2
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Rule: BufferExact
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Actual: Out2
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Expected: ExpectedOut2
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DescriptorSets:
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- Resources:
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- Name: Out1
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Kind: RWStructuredBuffer
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DirectXBinding:
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Register: 1
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Space: 0
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VulkanBinding:
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Binding: 2
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- Name: Out2
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Kind: RWStructuredBuffer
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DirectXBinding:
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Register: 2
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Space: 0
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VulkanBinding:
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Binding: 2
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...
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#--- end
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# REQUIRES: WaveSize_64
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# RUN: split-file %s %t
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# RUN: %dxc_target -T cs_6_6 -Fo %t.o %t/source.hlsl
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# RUN: %offloader %t/pipeline.yaml %t.o

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