SRF, PTL, NVL, MTL, LNL, GRR, GNR, CWF, ARL, ADL: Release platform updates

ADL/events/alderlake_goldencove_core.json

@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.39",
-    "DatePublished": "03/24/2026",
-    "Version": "1.39",
+    "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.40",
+    "DatePublished": "05/27/2026",
+    "Version": "1.40",
     "Legend": ""
   },
   "Events": [
@@ -5212,7 +5212,7 @@
       "UMask": "0x08",
       "EventName": "INST_RETIRED.REP_ITERATION",
       "BriefDescription": "Iterations of Repeat string retired instructions.",
-      "PublicDescription": "Number of iterations of Repeat (REP) string retired instructions such as MOVS, CMPS, and SCAS. Each has a byte, word, and doubleword version and string instructions can be repeated using a repetition prefix, REP, that allows their architectural execution to be repeated a number of times as specified by the RCX register. Note the number of iterations is implementation-dependent.",
+      "PublicDescription": "Number of iterations of Repeat (REP) string retired instructions such as MOVS, CMPS, and SCAS. Each has a byte, word, and doubleword version and string instructions can be repeated using a repetition prefix, REP, that allows their architectural execution to be repeated a number of times as specified by the RCX register. Note: Since the number of iterations within a REP instruction can be significantly affected by fast strings, this event may vary run to run and not match the architectural number of iterations (specified by RCX)",
       "Counter": "0,1,2,3,4,5,6,7",
       "PEBScounters": "1,2,3,4,5,6,7",
       "SampleAfterValue": "2000003",
@@ -5911,8 +5911,8 @@
       "EventCode": "0xc5",
       "UMask": "0x08",
       "EventName": "BR_MISP_RETIRED.RET",
-      "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS",
-      "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired.",
+      "BriefDescription": "This event counts the number of mispredicted ret instructions retired.",
+      "PublicDescription": "This event counts the number of mispredicted ret instructions retired.",
       "Counter": "0,1,2,3,4,5,6,7",
       "PEBScounters": "0,1,2,3,4,5,6,7",
       "SampleAfterValue": "100007",

ADL/events/alderlake_gracemont_core.json

@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.39",
-    "DatePublished": "03/24/2026",
-    "Version": "1.39",
+    "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.40",
+    "DatePublished": "05/27/2026",
+    "Version": "1.40",
     "Legend": ""
   },
   "Events": [
@@ -832,6 +832,56 @@
       "PDISTCounter": "NA",
       "Speculative": "1"
     },
+    {
+      "EventCode": "0x30",
+      "UMask": "0x00",
+      "EventName": "L2_REJECT_XQ.ANY",
+      "BriefDescription": "Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition.",
+      "PublicDescription": "Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition which likely indicates back pressure from the IDI link.  The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L2 write-back victims).",
+      "Counter": "0,1,2,3,4,5",
+      "PEBScounters": "0,1,2,3,4,5",
+      "SampleAfterValue": "200003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "Precise": "0",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "PDISTCounter": "NA",
+      "Speculative": "1"
+    },
+    {
+      "EventCode": "0x31",
+      "UMask": "0x00",
+      "EventName": "CORE_REJECT_L2Q.ANY",
+      "BriefDescription": "Counts the number of core requests (demand and L1 prefetchers) rejected by the L2 queue (L2Q) due to a full condition.",
+      "PublicDescription": "Counts the number of (demand and L1 prefetchers) core requests rejected by the L2 queue (L2Q) due to a full or nearly full condition, which likely indicates back pressure from L2Q.  It also counts requests that would have gone directly to the External Queue (XQ), but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link.  The L2Q may also reject transactions  from a core to ensure fairness between cores, or to delay a cores dirty eviction when the address conflicts incoming external snoops.  (Note that L2 prefetcher requests that are dropped are not counted by this event).  Counts on a per core basis.",
+      "Counter": "0,1,2,3,4,5",
+      "PEBScounters": "0,1,2,3,4,5",
+      "SampleAfterValue": "200003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "Precise": "0",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "PDISTCounter": "NA",
+      "Speculative": "1"
+    },
     {
       "EventCode": "0x34",
       "UMask": "0x01",
@@ -907,6 +957,31 @@
       "PDISTCounter": "NA",
       "Speculative": "1"
     },
+    {
+      "EventCode": "0x34",
+      "UMask": "0x06",
+      "EventName": "MEM_BOUND_STALLS.LOAD_L2_MISS",
+      "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which missed in the L2 cache.",
+      "PublicDescription": "Counts the number of cycles the core is stalled due to a demand load which missed in the L2 cache.",
+      "Counter": "0,1,2,3,4,5",
+      "PEBScounters": "0,1,2,3,4,5",
+      "SampleAfterValue": "1000003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "Precise": "0",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "PDISTCounter": "NA",
+      "Speculative": "1"
+    },
     {
       "EventCode": "0x34",
       "UMask": "0x07",
@@ -1007,6 +1082,31 @@
       "PDISTCounter": "NA",
       "Speculative": "1"
     },
+    {
+      "EventCode": "0x34",
+      "UMask": "0x30",
+      "EventName": "MEM_BOUND_STALLS.IFETCH_L2_MISS",
+      "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which missed in the L2 cache.",
+      "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which missed in the L2 cache.",
+      "Counter": "0,1,2,3,4,5",
+      "PEBScounters": "0,1,2,3,4,5",
+      "SampleAfterValue": "1000003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "Precise": "0",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "PDISTCounter": "NA",
+      "Speculative": "1"
+    },
     {
       "EventCode": "0x34",
       "UMask": "0x38",

ADL/events/alderlake_uncore.json

@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.39",
-    "DatePublished": "03/24/2026",
-    "Version": "1.39",
+    "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.40",
+    "DatePublished": "05/27/2026",
+    "Version": "1.40",
     "Legend": ""
   },
   "Events": [

ADL/events/alderlake_uncore_experimental.json

@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.39",
-    "DatePublished": "03/24/2026",
-    "Version": "1.39",
+    "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.40",
+    "DatePublished": "05/27/2026",
+    "Version": "1.40",
     "Legend": ""
   },
   "Events": [

ARL/events/arrowlake_crestmont_core.json

@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.19",
-    "DatePublished": "04/17/2026",
-    "Version": "1.19",
+    "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.20",
+    "DatePublished": "05/27/2026",
+    "Version": "1.20",
     "Legend": ""
   },
   "Events": [

ARL/events/arrowlake_lioncove_core.json

@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.19",
-    "DatePublished": "04/17/2026",
-    "Version": "1.19",
+    "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.20",
+    "DatePublished": "05/27/2026",
+    "Version": "1.20",
     "Legend": ""
   },
   "Events": [
@@ -4954,7 +4954,7 @@
       "UMaskExt": "0x00",
       "EventName": "INST_RETIRED.REP_ITERATION",
       "BriefDescription": "Iterations of Repeat string retired instructions.",
-      "PublicDescription": "Number of iterations of Repeat (REP) string retired instructions such as MOVS, CMPS, and SCAS. Each has a byte, word, and doubleword version and string instructions can be repeated using a repetition prefix, REP, that allows their architectural execution to be repeated a number of times as specified by the RCX register. Note the number of iterations is implementation-dependent.",
+      "PublicDescription": "Number of iterations of Repeat (REP) string retired instructions such as MOVS, CMPS, and SCAS. Each has a byte, word, and doubleword version and string instructions can be repeated using a repetition prefix, REP, that allows their architectural execution to be repeated a number of times as specified by the RCX register. Note: Since the number of iterations within a REP instruction can be significantly affected by fast strings, this event may vary run to run and not match the architectural number of iterations (specified by RCX)",
       "Counter": "0,1,2,3,4,5,6,7,8,9",
       "PEBScounters": "0,1,2,3,4,5,6,7,8,9",
       "SampleAfterValue": "2000003",

ARL/events/arrowlake_skymont_core.json

@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.19",
-    "DatePublished": "04/17/2026",
-    "Version": "1.19",
+    "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.20",
+    "DatePublished": "05/27/2026",
+    "Version": "1.20",
     "Legend": ""
   },
   "Events": [