config: enable Wildcat Lake in LPMD

[karanshukla]

Summary

Closes #123.

Add Wildcat Lake (family 6, model 0xD5/213) support: id_table[] entry plus a tuned config, same shape as #121 for Arrow Lake-H. This processor just released on the Dell XPS 13 2026, and the LPMD kept silently crashing at boot. The original workaround was to use --ignore-platform-check but I saw a PR and decided I could contribute as well to give the device a bit of a boost.

Topology: trust detect_cpu_topo(), not /sys/devices or lscpu -e

Verified on an Intel Core 5 320 (2 P-cores, 15W TDP). lscpu -e's L2-instance grouping (4 non-P cores sharing one L2 cluster) looks like a single Skymont-style E-core module, and /sys/devices/cpu_core/cpus / cpu_atom/cpus only give the P/atom split, not E vs L. Both are misleading here. Intel Reference for the CPU here.

Ran the daemon's own CPUID-based detection and it says otherwise:

Detected 2 Pcores, 0 Ecores, 4 Lcores, TDP 15W
CPU Config: 2P0E4L-15W

All 4 non-P cores fail is_cpu_in_l3() (no L3 in their CPUID leaf 4), so they classify as L, not E. There is no E-core tier on this platform, only P + L (Intel refers to them as Low Power Efficient or LP-E cores). A first draft of this config used ActiveEcores=ALL, which resolves to an empty CPU set on this topology and would leave Balanced/Powersaver mode with zero active cores. Caught by actually running it, not by reading the source.

Design

Same pattern as #121: P-cores parked in Balanced/Powersaver, WLT-driven EPP/EPB on the low-power tier.

Profile	Def	Mode	Active cores
Performance	-1	LPMD OFF	All (P+L)
Balanced	0	AUTO	L only
Power Saver	1	Force ON	L only

Balanced and Powersaver land on the same floor here since there's no third tier to drop to.

WLT states, all ActiveLcores=ALL:

State	WLT	EPP	EPB
UTIL_IDLE	0+1 (WLTTypeMask=3)	192 "balance_power"	8
UTIL_IDLE_SUSTAIN	2	64	4
UTIL_IDLE_BURSTY	3	128 "balance_performance"	6

WLTTypeMask=3 merges WLT 0/1 for the same reason as #121: this class of hardware oscillates between them fast enough that splitting them into separate EPP/EPB states is pure sysfs write churn for no benefit.

SoC Power Slider config omitted, not yet confirmed present on this sample via the int340x thermal driver.

Files changed

• src/lpmd_cpu.c - add model 0xD5 to id_table[]
• data/intel_lpmd_config_F6_M213.xml - new platform config
• data/Makefile.am - register config for install

Test plan

• Built from source (upower-devel, libnl3-devel needed, not in this repo's docs)
• Verified on Intel Core 5 320 (2P+4L, 15W TDP)
• Confirmed config file is found and parses (Found 3 config states)
• Confirmed Balanced mode parks P-cores via cgroup isolation (0,1 moved to isolated partition, 2-5 remain schedulable)
• Confirmed EPP/EPB apply per WLT state on transition (Set CPU2 EPP to 0xc0, etc.)
• Confirmed clean shutdown: EPP/EPB restored, cgroup partition reset to member, full CPU set restored