CUDA: XOR swizzle flash attn K,V smem fp16 tiles#25635
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Signed-off-by: ynankani <[email protected]>
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Overview
This PR adds XOR swizzling for K/V shared-memory tiles in the CUDA flash-attention fp16 MMA kernel (fattn-mma-f16.cuh), replacing row padding (+4) as the primary fix for shared-memory bank conflicts on cp.async stores and ldmatrix loads. On Turing+ (Ampere/Ada/Blackwell), when the K/V tile stride is a power-of-two ≥ 32, the kernel uses a pow2 stride with per-row XOR address remapping instead of padded row stride.
Additional information
Followed resource : https://lubits.ch/flash/Part-4
This change helped in improving perf for very high context, collected data for 65K depth
Performance DGX -SPARK
Performance RTX6000-PRO-BLACKWELL
Requirements