Add RISC-V board Bananapi BPI-F3 (SpacemiT K1 SoC) BSP Support #531
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Add RISC-V board Bananapi BPI-F3 (SpacemiT K1 SoC) BSP Support #531akifejaz wants to merge 1 commit into
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Add RISC-V supervisor support to the rv64/gnu port and provide a complete board support package for the BananaPi BPI-F3 (SpacemiT K1 SoC, X60 cores). Port changes (risc-v64/gnu): - Guard all CSR accesses with TX_RISCV_SMODE to select S-mode registers (sstatus/sepc/sie/sret) vs M-mode (mstatus/mepc/mie/mret) in context_save, context_restore, schedule, system_return, interrupt_control, and stack_build. - Add S-mode TX_INT_ENABLE/TX_DISABLE and inline TX_RESTORE macros to tx_port.h. - Add TX_RISCV_SMODE CMake option to CMakeLists.txt. BananaPi BPI-F3 BSP (example_build/bananapi-f3): - Boot flow: FSBL → OpenSBI (M-mode) → U-Boot (S-mode) → ThreadX - S-mode trap handler with context save/restore integration - SBI legacy ecall timer at 10 Hz (24 MHz timebase) - PLIC driver with S-mode context, stale-IRQ drain, and callbacks - PXA-compatible UART0 console (115200 8N1) - Linker script at 0x200000 load address Tested on risc-v board, BananaPi BPI-F3 hardware. Signed-off-by: Akif Ejaz <[email protected]>
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Add RISC-V supervisor support to the rv64/gnu port and provide a complete board support package for the BananaPi BPI-F3 (SpacemiT K1 SoC, X60 cores).
Port changes (risc-v64/gnu):
(sstatus/sepc/sie/sret) vs M-mode (mstatus/mepc/mie/mret) in
context_save, context_restore, schedule, system_return,
interrupt_control, and stack_build.
to tx_port.h.
BananaPi BPI-F3 BSP (example_build/bananapi-f3):
Tested on risc-v board, BananaPi BPI-F3 hardware.
Build and Test
Get your BPI-F3 board and Flash it normally as the process mentioned in BPI/Getting Started.
In order to build, use the following commands:
This should produce
kernel.elfandkernel.bin--
kernel.binorkernel.elfusing the following commandsdemo_threadx.clogs over UART.