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docs: complete data flow performance model for DreamZero training#81

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docs: complete data flow performance model for DreamZero training#81
zhangqin200182 wants to merge 3 commits into
dreamzero0:mainfrom
zhangqin200182:worktree-perf-model-doc

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Summary

Systematic trace of data volume, shapes, and formats through the entire DreamZero training pipeline, from DROID dataset to DiT forward pass.

Key Metrics (B=1, 8× Ascend 910 NPU)

Stage Data Size
Grid video input (3 views composited) 11.2 MB (bf16)
VAE latent 0.62 MB (45× compression)
DiT token sequence (3985 tokens × 5120 dim) 38.9 MB (bf16)
Per-layer DiT data movement (FSDP amortized) ~735 MB
HCCL total communication per step per card ~78.9 GB
Peak HBM ~19.5 GB (32%)
Trainable params ~86M (0.52% of 16.5B)

Contents

  • End-to-end data flow diagram with shapes at every stage
  • DreamTransform grid composition (3 camera views → 2×2 composite)
  • VAE/CLIP/T5 encoding sizes and compression ratios
  • Patch embedding and token assembly (Teacher Forcing)
  • 40-layer DiT per-component data movement breakdown
  • FSDP all-gather/reduce-scatter communication model
  • Gradient checkpointing analysis
  • LoRA parameter sizing
  • NPU HBM memory budget
  • Optimization opportunities
  • Comparison with original DreamZero paper setup

🤖 Generated with Claude Code

kevin and others added 3 commits July 21, 2026 10:18
Systematic trace of data volume, shapes, and formats through the entire
training pipeline: DROID dataset → DreamTransform grid composition →
VAE/CLIP/T5 encoding → patch embedding → token assembly → DiT 40-layer
forward → loss computation.

Key metrics per training step (B=1, 8× Ascend 910):
- Grid video input: 11.2 MB (3 views composited to 176×320)
- VAE latent: 0.62 MB (45× compression)
- DiT token sequence: 3985 tokens × 5120 dim = 38.9 MB (bf16)
- Per-layer data movement: ~735 MB (FSDP amortized per card)
- HCCL total communication: ~78.9 GB per step per card
- Peak HBM: ~19.5 GB (32% of 61.28 GB capacity)
- Trainable params: ~86M (0.52% of 16.5B total)

Includes FSDP all-gather/reduce-scatter patterns, gradient checkpointing
analysis, optimizer state sizing, and optimization opportunities.

Co-Authored-By: Claude <[email protected]>
Corrections from deep code tracing:
- Per-block params: 403.8M (not ~350M) — includes k_img, v_img in cross-attn
- LoRA: 19.2M params, 400 adapters (10/block — PEFT matches q,k,v,o
  in BOTH self_attn AND cross_attn by suffix)
- Total trainable: 113.9M (LoRA 19.2M + encoders/decoders 94.7M)
- Per-block bf16 size: 807.7 MB, per-card shard: ~101 MB
- HCCL total: ~148 GB bidirectional per step per card
- Gradient checkpointing: use_reentrant=False (not True)
- Added FSDP cleanup mechanism section (3-phase NPU workaround)

Co-Authored-By: Claude <[email protected]>
Complete comparison of LoRA vs full training across all dimensions:

Memory (per card, 8 NPU):
- LoRA: ~9.4 GB (15% HBM) → Full: ~34.6 GB (56% HBM)
- Main increase: optimizer states (+24.75 GB for 16.5B params)

HCCL Communication:
- LoRA: ~117 GB bidirectional → Full: ~231 GB bidirectional (1.98x)
- Reduce-scatter dominates: 57.7 GB vs 0.5 GB per card

Step Time:
- LoRA: ~32s → Full: ~40-55s (1.25-1.7x slower)
- Optimizer step dominates: 5-8s (16.5B params) vs 0.5-1s (114M)

Also covers:
- 16 NPU scenario (33% HBM, lower per-card comm)
- Checkpoint strategy (sharded: 8.25 GB/card, full: 66 GB)
- Decision matrix: LoRA vs Full trade-offs
- Data flow unchanged vs changed stages

Co-Authored-By: Claude <[email protected]>
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