Electronics & Instrumentation Engineering @ Dayananda Sagar College of Engineering, Bengaluru
Focusing on bare-metal embedded firmware and register-level STM32 programming
- STM32 Peripheral Driver Library: Modular bare-metal drivers for UART, I2C, Timers — built from register access, no HAL
- TX DMA: Non-blocking transmit to complement the RX DMA + Idle Line architecture already in production
- SPI Driver: Next peripheral on the roadmap after UART is fully complete
Building embedded systems from first principles:
GPIO → UART (IRQ + DMA) → I2C → Timers (Input Capture) → SPI → PWM → FreeRTOS
Embedded: C (bare-metal, register-level), ARM Cortex-M4, STM32F446RE, ESP32
Protocols: UART (DMA + Idle Line Detection), I2C (bare-metal, multi-byte burst), SPI (in progress)
Peripherals: TIM Input Capture, DMA, NVIC, USART, I2C, GPIO
Tools: STM32CubeIDE, GDB, ST-LINK, Logic Analyzer, Oscilloscope, Git
Hardware: Soldering, Digital Multimeter, 3D-printed prototype integration
Dual-MCU edge IoT system deployed on a 3D-printed RC car chassis. STM32F446RE runs a deterministic bare-metal sensor fusion pipeline — LSM6DS3 IMU over I2C, HC-SR04 ultrasonic via TIM5 Input Capture, NEO-6M GPS via USART1 IRQ ring buffer. Anomaly events are serialized using custom integer-to-string formatters (no sprintf) and forwarded to an ESP32 WiFi gateway over UART3.
Key engineering: gravity-vector LPF for orientation-independent vertical shock detection, non-blocking event-driven HC-SR04 measurement, 300ms cooldown debounce, I2C bus-lock recovery via CR1 SWRST at init.
Tech: C (bare-metal), STM32F446RE, ESP32, LSM6DS3, HC-SR04, NEO-6M, I2C, UART, TIM Input Capture, DMA
Register-level UART command-line interface on STM32F446RE. RX uses DMA1 Stream5 with Idle Line Detection — zero per-byte CPU overhead, packet boundary detected in hardware. ISR sets a flag; all parsing happens in the main loop. Includes stateful ESC sequence parser for arrow-key command history (last 5 commands), dynamic baud rate reconfiguration at runtime, and TIM2 interrupt-driven LED blink.
Key debug find: stale DMA interrupt flags in HIFCR must be cleared before re-enabling the stream — skipping this causes the stream to misbehave on re-arm after the first packet.
Tech: C (bare-metal), STM32F446RE, USART2, DMA1, TIM2, NVIC
📧 Email: [email protected]
🔗 LinkedIn: linkedin.com/in/adarsha-udupa-baikady-327a54219
📍 Location: Bengaluru, India
Learning in public. Building embedded systems the hard way.