Skip to content

RISC-V: Add INSN_DREF to memory read/write instructions#90

Open
a4lg wants to merge 1 commit into
masterfrom
riscv-opcode-dref
Open

RISC-V: Add INSN_DREF to memory read/write instructions#90
a4lg wants to merge 1 commit into
masterfrom
riscv-opcode-dref

Conversation

@a4lg

@a4lg a4lg commented Nov 18, 2022

Copy link
Copy Markdown
Owner

@a4lg
a4lg force-pushed the riscv-opcode-dref branch 4 times, most recently from a852c00 to 9404ae4 Compare November 19, 2022 11:57
@a4lg a4lg added the bug Something isn't working label Nov 19, 2022
@a4lg
a4lg force-pushed the riscv-opcode-dref branch 13 times, most recently from 89d5460 to b9a94e8 Compare November 26, 2022 00:28
@a4lg
a4lg force-pushed the riscv-opcode-dref branch 8 times, most recently from 0cb2f27 to 05fffe5 Compare December 2, 2022 03:27
@a4lg
a4lg force-pushed the riscv-opcode-dref branch 4 times, most recently from ab20a49 to 6c5011a Compare December 11, 2022 06:32
@a4lg
a4lg force-pushed the riscv-opcode-dref branch 4 times, most recently from 5992be8 to b169fda Compare January 7, 2023 02:32
@a4lg
a4lg force-pushed the riscv-opcode-dref branch 3 times, most recently from 299ed65 to 9858575 Compare January 16, 2023 08:39
@a4lg
a4lg force-pushed the riscv-opcode-dref branch 4 times, most recently from 66dac0f to 6dc8314 Compare January 30, 2023 00:26
@a4lg
a4lg force-pushed the riscv-opcode-dref branch 9 times, most recently from f7bfd52 to 5138b75 Compare February 7, 2023 02:55
@a4lg
a4lg force-pushed the riscv-opcode-dref branch 2 times, most recently from 9678ebc to a3325e9 Compare February 15, 2023 04:34
@a4lg
a4lg force-pushed the riscv-opcode-dref branch from a3325e9 to 24f8c6f Compare March 1, 2023 10:46
@a4lg
a4lg force-pushed the riscv-opcode-dref branch from 24f8c6f to 74129b9 Compare March 16, 2023 03:02
@a4lg
a4lg force-pushed the riscv-opcode-dref branch 2 times, most recently from 5e081ad to b364daf Compare August 1, 2023 03:40
@a4lg
a4lg force-pushed the riscv-opcode-dref branch 3 times, most recently from e0d32be to 239620b Compare August 3, 2023 05:59
@a4lg
RISC-V: Add INSN_DREF to memory read/write instructions
a2ca1a3 
This commit adds INSN_DREF flag (and optional size-related flag) to the
instructions that read/write the memory directly.  It however excludes
cache-related instructions that do synchronization of some sort but
otherwise don't touch the contents of the memory.

INSN_DREF and optional size flag are added to following instructions:

-   "cbo.zero" (from the 'Zicboz' extension)
-   All instructions from following custom extensions:
    -   'XTheadFMemIdx'
    -   'XTheadInt'
    -   'XTheadMemIdx'
    -   'XTheadMemPair'

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Add INSN_DREF and optional size
	flag on the instructions directly read/write memory.
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Reviewers

No reviews

Assignees

No one assigned

Labels

bug Something isn't working

Projects

None yet

Milestone

No milestone

Development

Successfully merging this pull request may close these issues.

1 participant

@a4lg