FPGA-Based Neural Network Accelerator

Overview

This project implements a Hardware-Software Co-Design workflow for accelerating Artificial Neural Networks (ANN) on FPGAs. It bridges the gap between high-level software models and low-level hardware implementation.

The system consists of a neural network trained in Python (PyTorch) for MNIST digit recognition, which is then quantized and mapped onto a custom RTL (Register Transfer Level) architecture designed in Verilog. The hardware accelerator performs Multiply-Accumulate (MAC) operations and ReLU activation in a deterministic hardware environment.

Key Features

• Custom RTL Design: Implemented MAC (Multiply-Accumulate) and ReLU units from scratch using Verilog HDL.
• Fixed-Point Arithmetic: Converted floating-point weights/biases to 16-bit fixed-point integers to optimize hardware resource usage.
• Memory Initialization: Automated generation of .txt memory files (Hexadecimal) for Verilog $readmemh integration.
• Bit-Perfect Verification: Achieved 100% correlation between the Python software model and the Vivado behavioral simulation.