Hardware Obfuscation Framework for DFG-to-Verilog Code Generation

📋 Project Overview

This project implements a comprehensive High-Level Synthesis (HLS) framework that converts Data Flow Graphs (DFG) into hardware-optimized Verilog code with advanced obfuscation techniques to prevent reverse engineering attacks on hardware accelerators. The framework employs brute-force resource optimization, scheduling algorithms, and self-referencing structural variants to generate 1000+ unique equivalent designs.

🎯 Key Features

• DFG to Verilog Conversion: Automated conversion of behavioral descriptions to RTL
• Resource Optimization: Brute-force analysis to find optimal adder/multiplier configurations
• Hardware Obfuscation: Two variants (16-bit partial, full obfuscation)
• Self-Referencing Variants: Generates 1000 unique structurally equivalent designs
• Multiple DSP Filters: FIR, IIR, FFT, DCT, IDCT, DWT, JPEG, MPEG, ARF, BPF, EWF, WDF
• Security: Protects against reverse engineering and IP theft

---

🏗️ Architecture

Workflow Pipeline

graph LR
    A[DFG Input] --> B[Resource Optimization]
    B --> C[HLS Scheduling]
    C --> D[Allocation & Binding]
    D --> E[Verilog Generation]
    E --> F[Obfuscation Engine]
    F --> G[Variant Generator]
    G --> H[1000 Unique Designs]

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Components

1. Resource Configuration Optimizer (optimal_cost_brust_force.py)

   • Analyzes all possible resource configurations
   • Calculates cost function: Cost = 0.5*(Area/Max_Area) + 0.5*(Delay/Max_Delay)
   • Provides top-3 optimal configurations
   • Default: Uses 3rd best configuration for security-performance balance

2. Verilog Code Generators

   • generate_dfg_to_verilog_code.py - Clean (unobfuscated) 32-bit
   • generate_dfg_to_verilog_16bit.py - 16-bit partial obfuscation
   • generate_dfg_to_verilog_fully_code_obf.py - Full obfuscation 32-bit

3. Variant Generation Engine

   • Verilog_pattern_generator.py - Generates 1000 unique structural variants
   • Verilog_varient_generator.py - Additional variant generation
   • Uses parity-based combinatorial obfuscation

---

📊 HLS Framework Details

Scheduling Algorithm

List-Based Scheduling with resource constraints:

• ASAP (As Soon As Possible) with dependencies
• Resource-aware allocation (multipliers, adders)
• Register minimization with reuse

Allocation Strategy

Resource Type	Area (μm²)	Delay (μs)	Notes
Multiplier	303.4976	264.9708	32-bit floating-point
Adder	75.4976	66.2428	32-bit floating-point
Register	0.7896	25.9108	State storage
MUX (2:1)	0.6390	12.7494	Input selection
DEMUX (1:2)	0.7373	22.4165	Output routing

Binding Mechanism

• Multipliers: Bound to M1, M2, ... Mn
• Adders: Bound to A1, A2, ... An
• Rotating allocation: Operations distributed across resources
• MUX/DEMUX sizing: Power-of-2 based on operation count

---

🔒 Obfuscation Techniques

1. Partial Obfuscation (16-bit)

Strategy: Hybrid approach

• Primary inputs: Odd/Even parity pool decoys
• Intermediate wires: Swap-based obfuscation
• Key size: 16 bits
  • 6 bits for primary input obfuscation
  • 10 bits for intermediate wire obfuscation

Example:

module FIR_obf(
    input wire [15:0] a, b, c, d,
    input wire [15:0] KEYINPUT,  // 16-bit key
    output wire [15:0] final_result1
);
    fp_mul1 mul1(.a(KEYINPUT[0] ? c : a), 
                 .b(KEYINPUT[1] ? b : d), 
                 .result(temp_result1));
    // Correct Key: 0101010101010101 (alternating pattern)
endmodule

2. Full Obfuscation (32-bit)

Strategy: All operations obfuscated

• Every input pair gets unique KEY bits
• Variable key size (auto-calculated)
• Maximum security with performance overhead

3. Obfuscation Selection Rules

Input Type	Decoy Pool	Pattern	Security Level
Both Primary	Odd/Even Parity	Position-based	High
Mixed (Primary + Intermediate)	Swap Strategy	Cross-reference	Medium
Both Intermediate	Available Wires	Dependency-safe	Medium-High

---

🎲 Self-Referencing Variant Generation

Mechanism

Creates 1000 unique structurally equivalent designs using:

1. Parity-Based Pools

   • Odd position inputs (a, c, e, g, ...) → Decoy from odd pool
   • Even position inputs (b, d, f, h, ...) → Decoy from even pool

2. Combinatorial Explosion Control

   • max_pool_size=3: Limits decoy choices per signal
   • Random sampling from total combination space
   • Example: 9 lines × 9 choices = 9⁹ = 387M combinations
   • Samples 1000 unique variants efficiently

3. Output Organization

   verilog_design_<FILTER>_obf_dataset_1000_samples_pattern/
   ├── Train_<FILTER>_obf_syn_locked_rnd_16_1_syn.v  (998 files)
   ├── Test_<FILTER>_obf_syn_locked_rnd_16_1_syn.v   (1 file)
   └── Validate_<FILTER>_obf_syn_locked_rnd_16_1_syn.v (1 file)
   

Applications

• GNN Training: Train graph neural networks to detect obfuscation
• Hardware Security Research: Analyze obfuscation effectiveness
• IP Protection: Generate diverse implementations of same design

---

🚀 Usage Guide

Step 1: Resource Optimization (Brute-Force)

python optimal_cost_brust_force.py

Input:

Enter the DFG input file name: FIR.txt
Enter the maximum number of resources (multipliers/adders): 4

Output:

=== Top 3 Lowest Cost Configurations ===
Rank 1: 2 Multipliers, 3 Adders, Cost=0.8234
Rank 2: 3 Multipliers, 2 Adders, Cost=0.8456
Rank 3: 2 Multipliers, 2 Adders, Cost=0.8792  ← SELECTED

Note: Framework uses 3rd best configuration for security-performance balance

Step 2: Generate Base Obfuscated Design

Option A: 16-bit Partial Obfuscation

python 16bit_obf.py

Option B: Full Obfuscation (32-bit)

python generate_dfg_to_verilog_fully_code_obf.py

Input:

Enter the DFG file path: FIR.txt
Enter number of adders: 2
Enter number of multipliers: 2

Output: FIR_obf.v with embedded obfuscation

Step 3: Generate 1000 Unique Variants

python Verilog_pattern_generator.py

Input:

Enter Verilog file path: FIR_obf.v
Number of unique samples to generate: 1000
Enter max pool size (press Enter for 3): 3

Output:

Detected module name: FIR_obf
Auto-detected multiplier results: [temp_result1, temp_result2, ...]
Odd position inputs (1,3,5,...): ['a', 'c', 'e', 'g']
Even position inputs (2,4,6,...): ['b', 'd', 'f', 'h']
Total possible unique variants: 387420489

Done — wrote 1000 unique variants to: verilog_design_FIR_obf_dataset_1000_samples_pattern

---

📂 Directory Structure

list_based_sched_code/
├── README.md                              # This file
├── CODE_EXPLANATION.md                    # Detailed code walkthrough
├── USAGE_GUIDE.md                         # Quick reference
├── COMBINATION_GUIDE.md                   # Variant generation guide
│
├── optimal_cost_brust_force.py           # Resource optimization
├── generate_dfg_to_verilog_code.py       # Unobfuscated generator
├── 16bit_obf.py                          # 16-bit obfuscation
├── generate_dfg_to_verilog_fully_code_obf.py  # Full obfuscation
├── Verilog_pattern_generator.py          # 1000 variant generator
├── Verilog_varient_generator.py          # Alternate variant tool
│
├── Benchmarks_hls_unobf_verilog_codes/   # Clean Verilog outputs
├── Benchmarks_hls_16bit_obf_verilog_codes/  # 16-bit obfuscated
├── Benchmarks_hls_fully_obf_verilog_codes/  # Full obfuscated
│
├── verilog_design_<FILTER>_obf_dataset_1000_samples_pattern/  # Variants
│
└── *.txt                                  # DFG input files
    ├── FIR.txt
    ├── IIRB.txt
    ├── FFT.txt
    ├── DCT.txt
    ├── IDCT.txt
    ├── DWT.txt
    ├── JPEG.txt
    ├── MPEG.txt
    ├── ARF.txt
    ├── BPF.txt
    ├── EWF.txt
    └── wdf.txt

---

📝 DFG Input Format

Data Flow Graphs use the format: operation, input1, input2, output

Example: FIR.txt

*, 0, 0, 1
*, 0, 0, 2
*, 0, 0, 3
+, 1, 2, 4
+, 3, 4, 5

Explanation:

• operation: * (multiply) or + (add)
• input1, input2: Node IDs (0 = primary input)
• output: Result node ID

Generated Operations:

temp_result1 = a * b        # mul1
temp_result2 = c * d        # mul2
temp_result3 = e * f        # mul3
temp_result4 = temp_result1 + temp_result2  # add1
final_result1 = temp_result3 + temp_result4  # add2

---

🔬 Supported DSP Filters

Filter	Operations	Inputs	Key Features
FIR	5	6	Finite Impulse Response
IIRB	3	4	Infinite Impulse Response (Basic)
FFT	8	8	Fast Fourier Transform
DCT	10	8	Discrete Cosine Transform
IDCT	10	8	Inverse DCT
DWT	4	4	Discrete Wavelet Transform
JPEG	27	16	JPEG Compression Core
MPEG	6	8	MPEG Video Processing
ARF	6	8	Adaptive Recursive Filter
BPF	6	8	Band-Pass Filter
EWF	8	8	Elliptic Wave Filter
WDF	8	8	Wave Digital Filter

---

🛡️ Security Analysis

Attack Mitigation

Attack Type	Mitigation Strategy	Effectiveness
Reverse Engineering	Ternary mux obfuscation	⭐⭐⭐⭐
SAT Attacks	Key-controlled signal paths	⭐⭐⭐⭐⭐
Brute Force Key	16-bit keyspace (65,536 combinations)	⭐⭐⭐
Machine Learning	1000 diverse structural variants	⭐⭐⭐⭐
Physical Probing	Logic locking at synthesis level	⭐⭐⭐

Key Properties

• Correct Key: Embedded in comments (for verification)
• Incorrect Key: Circuit produces wrong outputs
• Key Format: Binary string (MSB..LSB)
• Example: 0101010101010101 for alternating pattern

---

⚙️ Floating-Point Module Implementation

32-bit (IEEE 754 Single Precision)

module fp_mul1(
    input  wire [31:0] a,     // Sign[31] Exp[30:23] Mantissa[22:0]
    input  wire [31:0] b,
    output wire [31:0] result
);
    // Sign calculation
    wire sign_res = a[31] ^ b[31];
    
    // Exponent addition (bias correction)
    wire [7:0] exp_sum = a[30:23] + b[30:23] - 8'd127;
    
    // Mantissa multiplication (with implicit 1)
    wire [47:0] mant_prod = {1'b1, a[22:0]} * {1'b1, b[22:0]};
    
    // Normalization
    wire [22:0] mant_norm = mant_prod[47] ? 
                            mant_prod[46:24] : 
                            mant_prod[45:23];
    wire [7:0] exp_res = mant_prod[47] ? exp_sum + 1 : exp_sum;
    
    assign result = {sign_res, exp_res, mant_norm};
endmodule

📈 Performance Metrics

Typical Configuration (FIR Filter)

Metric	2M×2A	2M×3A	3M×3A
Total Area (μm²)	758.82	834.32	1062.32
Total Delay (μs)	264.97	198.73	198.73
Register Count	4	3	2
Cost Function	0.8792	0.8456	0.8234
Selected	✅ (3rd)	❌ (2nd)	❌ (1st)

Why 3rd Best?

• Balance between area, delay, and security
• Avoids predictable "optimal" implementation
• Harder for attackers to reverse-engineer resource allocation

---

🔧 Advanced Features

1. Auto-Detection

The framework automatically detects:

• Number of operations (multipliers, adders)
• Primary input count
• Intermediate wire dependencies
• Final output signals

2. Dependency Management

# Ensures correct scheduling
def dependencies_satisfied(node, produced_at):
    return all(produced_at.get(dep, None) is not None 
               for dep in node.dependencies)

3. Register Reuse

Minimizes register count by reusing storage:

# Only create register if data used beyond next cycle
if in1 != 0 and produced_at[in1] != time_step - 1:
    if in1 not in registers:
        registers[in1] = f'R{register_count}'
        register_count += 1

---

🧪 Verification & Testing

Functional Verification

1. Check Correct Key: Output should match unobfuscated design
2. Check Wrong Key: Output should differ
3. Synthesis Check: Yosys/Synopsys compatibility

Example Testbench:

module tb_FIR_obf;
    reg [15:0] a, b, c, d, e, f;
    reg [15:0] KEYINPUT;
    wire [15:0] result;
    
    FIR_obf dut(.*);
    
    initial begin
        // Test correct key
        KEYINPUT = 16'b0101010101010101;
        {a,b,c,d,e,f} = {16'd1, 16'd2, 16'd3, 16'd4, 16'd5, 16'd6};
        #100;
        // Test wrong key
        KEYINPUT = 16'b1111111111111111;
        #100;
    end
endmodule

Dataset Validation

Generated datasets have been validated for:

• ✅ Structural equivalence (same topology)
• ✅ Unique obfuscation patterns
• ✅ Correct train/test/validate split (998/1/1)
• ✅ GNN compatibility

---

📚 Related Documentation

• CODE_EXPLANATION.md: Detailed code walkthrough
• USAGE_GUIDE.md: Quick reference guide
• COMBINATION_GUIDE.md: Variant generation details

---

🔬 Research Applications

1. Hardware Security

• IP protection for DSP accelerators
• Anti-reverse-engineering for FPGAs/ASICs
• Secure hardware key storage

2. Machine Learning

• GNN training for obfuscation detection
• Subgraph pattern recognition
• Graph classification tasks

3. HLS Research

• Resource optimization algorithms
• Scheduling heuristics
• Area-delay tradeoff analysis

---

🚧 Current Limitations

1. Floating-Point Only: Integer arithmetic not implemented
2. Fixed Operations: Only multiply and add supported
3. No Pipeline: Single-cycle resource usage
4. Static Key: Key hardcoded at generation time

---

🔮 Future Enhancements

• Integer arithmetic support
• Dynamic key loading (external input)
• Pipeline scheduling
• Subtraction/division operations
• Multi-level obfuscation (nested keys)
• Automated equivalence checking
• Power analysis mitigation

---

📞 Support & Contribution

For questions, issues, or contributions:

1. Check existing documentation
2. Review code comments
3. Examine example outputs
4. Test with provided DFG files

---

📄 License

This project is for research and educational purposes. Please cite appropriately if used in publications.

---

🎓 Citation

If you use this framework in your research, please cite:

@misc{hls_obfuscation_framework,
  title={HLS Framework for DFG-to-Verilog with Hardware Obfuscation},
  author={Srinivasa Rao Dara, Dr. Dipanjan Roy , Dr. Ilaiah Kavati },
  year={2025},
  note={Hardware security framework with self-referencing variants}
}

---

🤖 LogicSafe-LLM (Experimental)

We provide two versions of the specialized hardware security model:

Model 1: Baseline LogicSafe-LLM

Standard HLS-to-Verilog with structural obfuscation.

• Dataset: llm_prepare_dataset.py
• Trainer: llm_trainer.py
• Inference: llm_inference.py

Model 2: LogicSafe-LLM v2 (Hybrid Engine)

Advanced model for custom security and optimization.

• Multi-Format: Understands DFG, CDFG, C, and SystemC.
• Custom Patterns: Takes any binary pattern (e.g., 1011001) as input.
• Optimal Ranks: Generates design based on specific cost Rank 1, 2, or 3.
• Dataset: logic_safe_v2_prepare_dataset.py
• Trainer: logic_safe_v2_trainer.py
• Inference: logic_safe_v2_inference.py

Research Goals

• Pattern Learning: Can an LLM learn to apply the "Parity Pool" strategy autonomously?
• Logic Equivalence: Ensuring AI-generated Verilog remains functionally identical to the DFG.
• Zero-Shot Obfuscation: Generating security patterns for completely new filters not seen in the training set.

---

📊 Quick Reference Card

Task	Command	Output
Find optimal config	python optimal_cost_brust_force.py	Top-3 configurations
Generate 16-bit obf	python 16bit_obf.py	<FILTER>_obf.v
Generate full obf	python generate_dfg_to_verilog_fully_code_obf.py	<FILTER>_obf.v
Generate 1000 variants	python Verilog_pattern_generator.py	1000 .v files
Clean generation	python generate_dfg_to_verilog_code.py	Unobfuscated .v

---

Created: December 2025
Version: 1.0
Status: Production Ready ✅