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Charged
RTL Design & Verification Engineer with practical expertise in ASIC/FPGA design flows for end-to-end integration IPs
- Hyderabad, India
- in/sreekash-us
Pinned Loading
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CDCL-Solver
CDCL-Solver PublicA small implementation of CDCL SAT solver that is used to solve 3SAT expressions
C++
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Mini-Stereo-Digital-Audio-Processor
Mini-Stereo-Digital-Audio-Processor PublicThis repository is a documentation only placeholder for an academic project focused on the ASIC design flow, covering stages from RTL design through physical implementation and GDS generation using…
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