Verilog RISC-V Processor

A 64-bit RISC-V (RV64I) processor implemented in Verilog featuring both a single-cycle processor and a 5-stage pipelined processor.

The project was developed as part of the Introduction to Processor Architecture course at IIIT Hyderabad.

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Features

Single-Cycle (Sequential) Processor

• RV64I 64-bit datapath
• Register file (32 × 64-bit)
• ALU
• Immediate generator
• Control unit
• Instruction memory
• Data memory
• Branch execution (BEQ)
• Complete module-level testbenches

Five-Stage Pipeline

• IF
• ID
• EX
• MEM
• WB

Pipeline support includes:

• Data forwarding
• Hazard detection
• Load-use stalls
• Control hazard handling
• MEM-to-MEM forwarding optimization

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Supported Instructions

Category	Instructions
Arithmetic	add, sub
Logical	and, or
Immediate	addi
Memory	ld, sd
Branch	beq

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Project Structure

.
├── sequential/
├── pipelined/
├── project_report.pdf
└── README.md

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Architecture

Single-Cycle Datapath

• Program Counter
• Instruction Memory
• Register File
• Immediate Generator
• Control Unit
• ALU
• Data Memory
• Write-back Multiplexer

Pipeline Stages

Instruction Fetch
        ↓
Instruction Decode
        ↓
Execute
        ↓
Memory Access
        ↓
Write Back

Pipeline registers:

• IF/ID
• ID/EX
• EX/MEM
• MEM/WB

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Hazard Handling

The pipelined implementation supports:

• EX → EX forwarding
• MEM → EX forwarding
• Load-use hazard detection
• One-cycle pipeline stalls
• MEM → MEM forwarding for load-store sequences

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Testing

Each hardware module was verified independently before system integration.

Verified components include:

• Program Counter
• Register File
• ALU
• ALU Control
• Immediate Generator
• Control Unit
• Data Memory
• Pipeline Registers
• Full Processor Integration

Simulation was performed using:

• Icarus Verilog
• GTKWave

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Results

Implemented both:

• Single-cycle RV64I processor
• Five-stage pipelined RV64I processor

with successful execution of supported instruction sequences and verification through simulation waveforms and automated testbenches.

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Technologies

• Verilog HDL
• Icarus Verilog
• GTKWave

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Documentation

The complete design, implementation details, verification methodology, and pipeline analysis are available in:

📄 project_report.pdf

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Authors

• Shriya Kansal
• Prathish Ghosh
• Kavya Veer