[RISCV] Introduce RVI AME (standard, pre-ratification) backend support - #22
[RISCV] Introduce RVI AME (standard, pre-ratification) backend support#22vismaysur wants to merge 28 commits into
Conversation
|
Hello @vismaysur 👋 Thank you for submitting a Pull Request (PR) to the LLVM Project. Since this is your first PR, here are a few useful links covering our main contribution policies and review practices.
Please reply to this message to confirm that you have read these policies, especially the LLVM AI Tool Use Policy, and that any AI tool usage has been noted in the PR description. Frequently asked questionsHow do I add reviewers? This PR will be automatically labeled, and the relevant teams will be notified. For some parts of the project, reviewers may also be added automatically. You can also add reviewers manually using the Reviewers section on this page. If you cannot use that section, it is probably because you do not have write permissions for the repository. In that case, you can request a review by tagging reviewers in a comment using What if there are no comments? If you have not received any comments on your PR after a week, you can request a review by pinging the PR with a comment such as “Ping”. The common courtesy ping rate is once a week. Please remember that you are asking for volunteer time from other developers. Are any special GitHub settings required to contribute to LLVM? We only require contributors to have a public email address associated with their GitHub commits, see this section of LLVM Developer Policy for details. If you have questions, feel free to leave a comment on this PR, or ask on LLVM Discord or LLVM Discourse. Thank you, |
|
A few important observations / notes:
Just a detail to keep note of: if a stride operand is later added to the spec, we will not need to repack data in memory into tiles. |
12d2b78 to
36036f7
Compare
vismaysur
changed the title
e7c4297 to
8d7801d
Compare
b1e3edf to
5c844e7
Compare
5c844e7 to
c28b72e
Compare
b5dac9e to
a4a3978
Compare
a4a3978 to
2cc830c
Compare
Good catch. We will keep our design aligned with the RVI specification and make the corresponding changes if the specification is updated. |
|
Please rebase the PR. I will start the review today. |
2cc830c to
b9c7652
Compare
|
Note: BOSCAME backend seems to instruction select LLVM IR to pseudo instructions (with immediate operands) which are then directly printed as asm, with no path (as i understand it) to MCInstr encodings / .o output. it has real instruction encodings but these are only reachable from .s or .o inputs, not from LLVM IR (please clarify if my understanding is incorrect). Since M/Acc indices are already assigned by MLIR before they reach LLVM, so encoding them as immediates (rather than encoding register class operands) lets ISel lower straight to the real, bit-encoded instruction. I took a slightly different path in this backend of omitting the pseudo instructions altogether, instead encoding real instructions with immediate operands, enabling a single path from LLVM IR -> MCInstr with real encodings -> both .o and .s outputs. |
…opsrun test (RuyiAI-Stack#4) Fix three issues found on RISC-V: 1. Fix use-after-free in block walk (Visitors.h) When walking blocks with ReverseDominanceIterator, the Traversal object returned by Iterator::makeIterable(region) was passed as a temporary directly to llvm::make_early_inc_range(). The temporary was destroyed at the end of the full expression while iterators from make_early_inc_range still referenced it. Store the result in a local variable with auto&& to extend the lifetime of the temporary and bind lvalue references for ForwardIterator. 2. Fix Shape dialect CstrBroadcastableOp fold and cast canonicalization Extend getShapeVec to look through tensor.cast operations so that folds can resolve shapes behind casts inserted by earlier canonicalization passes (e.g., ShapeOfOpToConstShapeOp). Add a new fold check in CstrBroadcastableOp::fold that recognizes broadcasting is trivially valid when at most one operand is non-scalar (resolved via getShapeVec). Rewrite CanonicalizeCastExtentTensorOperandsPattern to use modifyOpInPlace instead of replaceOpWithNewOp to avoid issues with op builder template instantiation. 3. Fix opsrun.py test invocation pattern for multithreaded_tests.py Convert direct test_foo() calls to run(test_foo) so that copy_and_update in multithreaded_tests.py properly strips them during import, preventing JIT execution at module load time which crashes on RISC-V due to R_RISCV_HI20 relocation range limits.
Co-authored-by: Cursor <[email protected]>
60839cf to
0f1daf0
Compare
8 participants
This PR adds initial RISC-V AME backend support.
Tasks/Deliverables:
AME_NUM_M_REGSandAME_NUM_ACC_REGS).ll->.sand.ll->.o) and llvm-mc (.s->.o).Closes #21