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perf(EPv2): update EPv2 combine tune config#500

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kawhil-amd wants to merge 4 commits into
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kawhil-amd:perf_gfx1250
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perf(EPv2): update EPv2 combine tune config#500
kawhil-amd wants to merge 4 commits into
ROCm:mainfrom
kawhil-amd:perf_gfx1250

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kawhil-amd and others added 2 commits July 24, 2026 09:40
…irectly

Replace the two-phase comb_bar inter-block signaling chain with direct
xdb_mem spinning from all blocks. Removes atomic counting, final cleanup
spin, and reduces Stage 1 barrier code from ~30 lines to ~14 lines.

Co-Authored-By: Claude Opus 4.6 <[email protected]>
@kawhil-amd kawhil-amd closed this Jul 24, 2026
The epoch bump is the only thing advancing xdb_flag; without it the
second combine invocation sees stale xdb_mem == xdb_cur_flag and the
entry barrier becomes a no-op, reading unready data. Place the bump
after fx.barrier() so all blocks have consumed xdb_cur_flag first.

Co-Authored-By: Claude Opus 4.6 <[email protected]>
@kawhil-amd kawhil-amd reopened this Jul 24, 2026
Gather combine reads from remote peer memory via xGMI (uncached);
no local L2 stale entries to invalidate. The original code never had
this fence — it was incorrectly added during the comb_bar elimination.

Co-Authored-By: Claude Opus 4.6 <[email protected]>
@kawhil-amd kawhil-amd changed the title perf(EPv2): update gfx1250 combine tune config perf(EPv2): update EPv2 combine tune config Jul 24, 2026
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