Skip to content
View Hajjy22's full-sized avatar
🎯
Focusing
🎯
Focusing

Block or report Hajjy22

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Hajjy22/README.md
Typing SVG

Embedded Systems · IoT · ASIC / FPGA  ·  INPT Graduate 2025  ·  Rabat, Morocco 🇲🇦


👨‍💻 About

  • 🎓 Embedded Systems Engineer, graduated from INPT (2025)
  • 🔬 Previously at Siemens EDA — low-power ASIC design
  • 🏆 Orange Summer Challenge 2024 winner
  • ⚡ Working across the stack: embedded firmware, IoT connectivity, and custom digital hardware (RISC-V cores, CNN accelerators, IP)

🛠️ Tech Stack

Hardware / RTL

SystemVerilog Verilog VHDL UVM Vivado Quartus

Embedded / IoT

C C++ STM32 ESP32 FreeRTOS MQTT Python

🚀 Featured Work

Project Highlights
🖥️ AtlasRV32 32-bit RISC-V, 5-stage pipeline, hazard detection & forwarding · Artix-7 FPGA
🧠 CNN Accelerator 1024×1024 convolution @ 206 MHz · ASIC flow, 4.85 ns clock
SPEF Profiler Low-power analysis tool built at Siemens EDA
🔌 I2C Master IP Avalon interface, Nios II, 90%+ functional coverage

📊 GitHub Stats

Open to opportunities · Available for freelance work · Always learning

Pinned Loading

  1. AtlasRV-32-bit-RISC-V-Pipelined-Processor AtlasRV-32-bit-RISC-V-Pipelined-Processor Public

    AtlasRV32 — 32-bit RISC-V pipelined processor with hazard detection and data forwarding, synthesized on Artix-7 FPGA

    SystemVerilog 1