I’m an engineering enthusiast with a strong foundation in Electrical & Electronic Engineering and currently studying Software Engineering at Tampere University of Applied Sciences, Finland.
My passion lies at the intersection of embedded systems & software development, firmware development, digital design, and ASIC/FPGA workflows — and I’m continuously expanding my skills into software development to become a well‑rounded engineer.

I enjoy building systems that blend hardware and software, and I’m actively looking to contribute to embedded system development, firmware projects, and digital design/ASIC-related work to gain deeper hands‑on experience while contributing meaningfully to real projects.

• 🎓 Bachelor's Degree in Software Engineering (Ongoing) | Tampere University of Applied Sciences, Finland

• 🎓 B.Sc. in Electrical & Electronic Engineering | Sir John Kotelawala Defence University, Sri Lanka

• 🎓 Specialized Courses — University of Moratuwa, Sri Lanka

  • Fundamentals of Digital System Design
  • SystemVerilog for ASIC–FPGA Design & Simulation

• 🔧 Strong interest in:

  • Embedded Systems
  • Firmware Development
  • Digital Design
  • ASIC/FPGA Design Flow
  • Embedded Software
  • Low‑level programming
  • Hardware‑Software integration
  • Web development (as an additional skillset)

• 📘 Completed specialized courses from University of Moratuwa, Sri Lanka:

  • Fundamentals of Digital System Design
  • SystemVerilog for ASIC–FPGA Design & Simulation

• 🌱 Currently learning & improving:

  • Microcontroller programming
  • RTOS concepts
  • C/C++ for embedded systems
  • SystemVerilog & ASIC flow
  • Python for automation
  • Web development (HTML, CSS, JS) as a complementary skill

• 🤝 Open to collaborate on:

  • Embedded system development
  • Firmware projects
  • Digital design / ASIC flow
  • Software development projects
  • Any hands‑on engineering work that helps me grow

• C / C++
• Microcontrollers (ARM, AVR, ESP32 basics)
• UART, SPI, I2C fundamentals
• Interrupts, timers, peripherals
• Bare‑metal programming basics

• SystemVerilog
• RTL design
• Synthesis & PnR concepts
• Synopsys Design Compiler
• Synopsys IC Compiler II
• SAED 32nm library
• Timing, area, and power analysis

• HTML, CSS, JavaScript
• Python
• Java
• Git & GitHub
• Linux environment

• VS Code
• MATLAB
• Synopsys DC / ICC2
• ModelSim
• kLayout
• Git

Complete RTL‑to‑GDSII flow using SAED 32nm library
Synthesis, PnR, timing, area & power analysis
👉 View Repository

Designed to authenticate a 4‑bit security code using a combination of:

• AXI‑style Parallel‑to‑Serial (P2S) data conversion
• Finite State Machines (FSMs) — both Mealy and Moore versions
• Bit‑by‑bit verification logic
• Unlock/Incorrect signaling

👉 View Repository

A simple FPGA‑based mini calculator designed to multiply two single‑digit numbers (0–9) and display the result on a dual 7‑segment display. The design flow follows a structured hardware‑design approach:

• Building basic arithmetic blocks (1‑bit and 8‑bit adders)
• Constructing a 4‑bit multiplier using ripple‑carry adders
• Designing a 7‑segment decoder for display output
• Integrating all modules into a complete top‑level calculator system.

👉 View Repository

This project implements a traffic light controller using SystemVerilog, designed as a multi‑phase digital design exercise. This system models a realistic two‑road traffic junction with priority logic, amber‑light timing, and safe state transitions. 👉 View Repository

Built using HTML, CSS (Flexbox, Grid), and JavaScript
👉 View Repository
👉 Live Demo

A responsive, interactive weather dashboard that visualises past weather data from the Open-Meteo API. Built with plain HTML, CSS, and JavaScript
👉 View Repository
👉 Live Demo

• 📧 Email: [email protected]
• 💼 LinkedIn: Geethika Bandara Jayasekara