Tutorial at IEEE ISCAS 2026 on deploying spiking neural networks to FPGA hardware using the Neuromorphic Intermediate Representation (NIR).
Neuromorphic computing (NC) with spiking neural networks (SNNs) promises lower latency and power compared to conventional dense architectures, making it attractive for edge AI. However, the field suffers from a fragmented ecosystem: individual works are tied to specific models, simulators, and toolchains, and the gap between software simulation and hardware realization introduces subtle numerical divergences that are hard to track down.
NIR addresses this by formalizing SNN computations as platform-independent graphs of dynamical systems -- similar to what ONNX does for conventional ML. NIR is already supported by hardware platforms like BrainScaleS, Intel Loihi, SynSense Speck/Xylo, and SpiNNaker2, and by software frameworks like Sinabs and Norse.
In this tutorial, we show how to go from a trained SNN all the way to running hardware on an FPGA, using NIR2FPGA: a compilation framework that generates streaming dataflow accelerators from NIR graphs via SpinalHDL. The key idea is that by designing around NIR, we can shorten the representational distance between the model and the hardware, and verify behavioral consistency at every step.
| Time | Topic | Presenter(s) |
|---|---|---|
| 08:30 | Welcome | Michail Rontionov |
| 08:45 | Neuromorphic Engineering and Design Approaches | Charlotte Frenkel |
| 09:05 | Neuromorphic Computing on FPGAs | Nassim Beladel |
| 09:20 | Neuromorphic Intermediate Representation (NIR) | Jens E. Pedersen |
| 09:30 | Hands-on: Defining, Training & Exporting SNNs | Jens E. Pedersen & Michail Rontionov |
| 10:00 | Coffee Break | |
| 10:30 | NIR2FPGA | Michail Rontionov |
| 10:45 | SpinalHDL Introduction | Francisco Ayala Le Brun |
| 11:00 | Hands-on: Livecode NIR2FPGA, LIF in SpinalHDL, RTL MNIST SNN | Michail Rontionov |
| 11:45 | Thank you, and goodbye! | All |
- Michail Rontionov (University of Southampton) -- NIR2FPGA, hands-on exercises
- Jens Egholm Pedersen (Technical University of Denmark) -- NIR, SNNs in JAX
- Charlotte Frenkel (Delft University of Technology) -- NC introduction and design approaches
- Francisco Ayala Le Brun -- SpinalHDL
- Nassim Beladel (ETH Zurich) -- NC on FPGAs
- NIR2FPGA paper: Rontionov et al., Generating Dataflow Accelerators from the Neuromorphic Intermediate Representation To be announced
- NIR: neuroir.org -- Neuromorphic Intermediate Representation
- Code: github.com/mrontio/nir2fpga