ECE undergrad at PES University (Class of 2027). I work at the intersection of silicon and deep learning, with and interest towards highly integrated DL applications in hardware engineering.
- Open-Frame-gen: Real-Time Video Frame Interpolation on Constrained Consumer Hardware — JCSSE 2026, sole presenter (IEEE Xplore indexing pending). A 90K-parameter Nano CNN delivering 101 FPS on an RTX 3050 — 12x the throughput of RIFE HDv3, with 60x fewer parameters and 10x less VRAM.
- Omni-RISC — an RV32IM CPU fused with a SIMT GPU on one FPGA. 5-stage pipeline, M-mode privileged architecture, 53/54 on the official riscv-arch-test suite, plus a 2-core cache-coherent research rig (snooping MSI, LR/SC spinlocks). Synthesized end-to-end on an Artix-7.
- VFI-HLS — the hardware side of Open-Frame-gen. Hand-written RTL for the model's CNN backbone and warp+blend stage, verified bit-exact against a numpy golden reference, synthesized on FPGA.
- ascon-dlsca — power side-channel analysis on a masked ASCON-128 core, captured on a ChipWhisperer CW305/CW-Lite setup, with a byte-exact reference oracle verifying every trace.We aim to guess the key using a trained ml model on the setup.
- MultiCore RISC-V — an earlier 4-core RV32I processor project; the pipeline and coherence ideas here fed directly into Omni-RISC.
- ATLAS — an RL bipedal locomotion benchmarking framework for the Cassie platform, part of my capstone. (Private for now)