Add tiled systolic-array matmul support for OS and WS

[nervestop2]

修改内容：

• 为脉动阵列增加 OS 和 WS 模式下的分块矩阵乘法支持
• 支持沿 K 维对多个 4x4 tile 做累加执行
• 增加并验证 4x8 x 8x4 的端到端测试

验证情况：

• 测试目标：ctest_systolic_matmul_4x8_8x4
  日志说明指令4x8_8x4能顺利编译成2次执行，bfp_ws_first 和bfp_ws_last。测试结果也PASS
  [verilator sim] [instr 0] mvin_a_tile0 ptr=0x80003840 bank=0 depth=4 stride=1
  [verilator sim] [instr 1] mvin_b_tile0 ptr=0x800038c0 bank=1 depth=4 stride=1
  [verilator sim] [instr 2] bfp_ws_first op1_bank=0 op2_bank=1 wr_bank=2 iter=4 config[2:0]=0x3
  [verilator sim] [instr 3] mvin_a_tile1 ptr=0x80003880 bank=0 depth=4 stride=1
  [verilator sim] [instr 4] mvin_b_tile1 ptr=0x80003900 bank=1 depth=4 stride=1
  [verilator sim] [instr 5] bfp_ws_last op1_bank=0 op2_bank=1 wr_bank=2 iter=4 config[2:0]=0x7
  [verilator sim] [instr 6] mvout ptr=0x80003740 bank=2 depth=4 stride=1
  [verilator sim] [instr 7] fence
  [verilator sim] output_matrix =
  [verilator sim] 27252 22036 11089 27480
  [verilator sim] 34675 27701 29213 38586
  [verilator sim] 28397 27587 24762 39769
  [verilator sim] 27343 21374 14741 34213
  [verilator sim] expected_matrix =
  [verilator sim] 27252 22036 11089 27480
  [verilator sim] 34675 27701 29213 38586
  [verilator sim] 28397 27587 24762 39769
  [verilator sim] 27343 21374 14741 34213
  [verilator sim] systolic_matmul_4x8_8x4_ws PASSED

[shirohasuki]

Thanks for your time! I will do a quick review.

[shirohasuki]

Thank you so, so much for your work. I think we might need a README to explain the implementation of ball (no AIGC). To be honest, all these variables are a bit overwhelming.

[shirohasuki]

What are these disassembly files used for? Are they necessary?

[shirohasuki]

Please run pre-commit before committing.

[shirohasuki]

Have you do filecheck, these seem are not right.

[shirohasuki]

Nice progress.