"I specialize in designing and researching solutions for building reliable and accessible embedded systems."

I am a 3rd-year Computer Engineering student at VNUHCM-UIT (GPA: 8.55/10). I dedicate a lot of my time to designing frameworks to support the construction of reliable, lightweight, and highly applicable embedded systems. My current goal is to perfect the μEDP event-driven programming framework and move towards developing the μE-OS event-driven operating system with features referenced and modified from Linux.

• Current Focus: Developing μEDP - a small single-stack non-preemptive RTC event-driven programming framework for embedded systems.
• Core Philosophy: True system control comes from understanding the synergy between bussiness logic and deterministic behaviour.
• Languages: Vietnamese (Native), English (IELTS 7.0 - Proficient).

Languages	Hardware & PCB	Peripherals	Tools & Quality

Challenges: Hardware-Agnosticism (Zero-Touch Porting), Real-Time Determinism, Resource Isolation under Heavy Load, Non-intrusive System Observability.

• Architected a 3-layer decoupled framework (App-Core-PAL), enabling "Zero-Touch Porting" across STM32, ESP32, and Linux POSIX simulation. The core remains 100% unchanged while hardware-specific implementations are isolated in the PAL layer.
• Engineered a Unified Messaging System using Architecture-Aware Static Memory Pools (supporting 32/64-bit adaptively). Implemented Zero-Copy Reference Passing and an ISR Signal Bridge to ensure memory safety and data integrity without dynamic allocation (malloc-free).
• Optimized an O(1) Bitmask Scheduler enhanced with a Priority Escalation mechanism. This ensures critical task response at message boundaries, effectively mitigating task starvation in non-preemptive environments.
• Developed a non-intrusive logging architecture (Itnlog) based on Out-Context Execution (OCE). This allows high-frequency system snapshots (Task/Sig/FSM/TSM) to be recorded in nanoseconds and dumped during CPU idle time, preserving system timing and avoiding "Heisenbugs."
• Validated architectural compliance against QP/C SRS standards, ensuring the framework meets industrial-grade requirements for Active Object patterns and deterministic event delivery.

Challenges: Register-level Optimization, Class 0.5s Accuracy, HIL Testing, High-EMI Industrial Robustness.

• Implemented a Self-Healing Clock Tree with CSS to ensure 24/7 operation in high-EMI industrial environments.
• Developed register-level drivers for reliable SPI communication (Ping-Pong logic & Core Systick interference) compatible with Class 0.5s accuracy for the ADE7758 IC.
• Planned rigorous verification using SIL (Software-In-the-Loop) and developed a custom HIL Test-Jig using MCP4728 IC to simulate 3-phase power faults.

Challenges: 96ksps/24-bit Signal Integrity, Mixed-Signal PCB Design, Low-jitter Clock Trees.

• Architected a 24-bit/96ksps sampling engine using an external PCM1808 ADC and a custom Pierce Oscillator (74HCU04 IC) for jitter-free synchronization.
• Designed a dual-stage analog front-end using TL072IDT Op-Amps with 1MΩ & 2.2KΩ high-impedance inputs for TCT40-16R ultrasonic sensors (20kHz-45kHz), 10KΩ & 1KΩ high-impedance inputs for the MAX9812 amplified microphone module.
• Integrated a smart mechanical MUX to switch between MAX9812 & TCT40-16R sensors and PJ-342S 3.5mm audio jack for external computer connections.
• Implemented a split ground plane with local bridge to remove crosstalk noise from the Wi-Fi module to the Analog area, ensuring 24-bit signal integrity.