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Fix rawBufferVectorLoad/Store to widen min precision types to 32-bit #8274

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Merged
alsepkow merged 14 commits into from
Mar 31, 2026
Merged

Fix rawBufferVectorLoad/Store to widen min precision types to 32-bit #8274

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e13d0dc
Fix rawBufferVectorLoad/Store to widen min precision types to 32-bit
alsepkow Mar 18, 2026
ddeb1bd
Merge remote-tracking branch 'upstream/main' into user/alsepkow/fix-m…
alsepkow Mar 25, 2026
9defa02
Fix min16uint debug test to accept named SSA values
alsepkow Mar 26, 2026
b9f249a
Fix min16int_vec and min16float_vec debug tests for named SSA values
alsepkow Mar 26, 2026
7c95fb0
Address review: extract helpers, simplify code, shorten comments
alsepkow Mar 26, 2026
4302236
Apply suggestions from code review
alsepkow Mar 26, 2026
8e7c6fb
Update lib/HLSL/HLOperationLower.cpp
alsepkow Mar 26, 2026
41f37f9
Address review: refactor widenMinPrecisionType, extend to RawBufferStore
alsepkow Mar 30, 2026
df53605
Remove redundant comment on widenMinPrecisionType
alsepkow Mar 30, 2026
d6b3294
Trim verbose comments to explain why, not what
alsepkow Mar 31, 2026
14396ae
Rename test to min_precision_raw_load_store.hlsl
alsepkow Mar 31, 2026
81a1f81
Revert accidental submodule and unrelated file changes
alsepkow Mar 31, 2026
d7a0760
Fix min precision store widening: scope to ByteAddressBuffer only
alsepkow Mar 31, 2026
52a7193
Fix min precision store widening for ByteAddressBuffer scalars
alsepkow Mar 31, 2026
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52 changes: 50 additions & 2 deletions lib/HLSL/HLOperationLower.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4322,6 +4322,24 @@ static SmallVector<Value *, 10> GetBufLoadArgs(ResLoadHelper helper,
return Args;
}

static bool isMinPrecisionType(Type *EltTy, const DataLayout &DL) {
return !EltTy->isIntegerTy(1) &&
DL.getTypeAllocSizeInBits(EltTy) > EltTy->getPrimitiveSizeInBits();
}

// Widens a min precision element type to its 32-bit equivalent (i32 or f32).
// Returns the original type if not min precision.
static Type *widenMinPrecisionType(Type *EltTy, Type *VecOrScalarTy,
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IRBuilder<> &Builder, const DataLayout &DL) {
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if (!isMinPrecisionType(EltTy, DL))
return VecOrScalarTy;
Type *WideTy = EltTy->isFloatingPointTy() ? (Type *)Builder.getFloatTy()
: (Type *)Builder.getInt32Ty();
if (VecOrScalarTy->isVectorTy())
return VectorType::get(WideTy, VecOrScalarTy->getVectorNumElements());
return WideTy;
}

// Emits as many calls as needed to load the full vector
// Performs any needed extractions and conversions of the results.
Value *TranslateBufLoad(ResLoadHelper &helper, HLResource::Kind RK,
Expand All @@ -4338,9 +4356,16 @@ Value *TranslateBufLoad(ResLoadHelper &helper, HLResource::Kind RK,
Type *EltTy = Ty->getScalarType();
const bool is64 = (EltTy->isIntegerTy(64) || EltTy->isDoubleTy());
const bool isBool = EltTy->isIntegerTy(1);
// Min precision alloc size exceeds prim size. Use the widened type.
const bool isMinPrec = isMinPrecisionType(EltTy, DL);
Type *OrigEltTy = EltTy;
// Values will be loaded in memory representations.
if (isBool || (is64 && isTyped))
EltTy = Builder.getInt32Ty();
if (isBool || (is64 && isTyped) || isMinPrec) {
if (isMinPrec && EltTy->isFloatingPointTy())
EltTy = Builder.getFloatTy();
else
EltTy = Builder.getInt32Ty();
}
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// Calculate load size with the scalar memory element type.
unsigned LdSize = DL.getTypeAllocSize(EltTy);
Expand Down Expand Up @@ -4454,6 +4479,14 @@ Value *TranslateBufLoad(ResLoadHelper &helper, HLResource::Kind RK,
retValNew = Builder.CreateICmpNE(
retValNew, Constant::getNullValue(retValNew->getType()));

// Truncate widened min precision loads back to original type.
if (isMinPrec) {
if (OrigEltTy->isIntegerTy())
retValNew = Builder.CreateTrunc(retValNew, Ty);
else
retValNew = Builder.CreateFPTrunc(retValNew, Ty);
}

helper.retVal->replaceAllUsesWith(retValNew);
helper.retVal = retValNew;

Expand Down Expand Up @@ -4574,6 +4607,21 @@ void TranslateStore(DxilResource::Kind RK, Value *handle, Value *val,
val = Builder.CreateZExt(val, Ty);
}

// Widen min precision types to i32/f32 for RawBufferVectorStore.
if (opcode == OP::OpCode::RawBufferVectorStore) {
const DataLayout &DL =
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OP->GetModule()->GetHLModule().GetModule()->getDataLayout();
Type *WideTy = widenMinPrecisionType(EltTy, Ty, Builder, DL);
if (WideTy != Ty) {
if (EltTy->isFloatingPointTy())
val = Builder.CreateFPExt(val, WideTy);
else
val = Builder.CreateSExt(val, WideTy);
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EltTy = WideTy->getScalarType();
Ty = WideTy;
}
}

// If RawBuffer store of 64-bit value, don't set alignment to 8,
// since buffer alignment isn't known to be anything over 4.
unsigned alignValue = OP->GetAllocSizeForType(EltTy);
Expand Down
16 changes: 8 additions & 8 deletions tools/clang/test/HLSLFileCheck/dxil/debug/min16/min16float_vec.hlsl
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Original file line number Diff line number Diff line change
Expand Up @@ -16,20 +16,20 @@ void main()
{
Foo foo = buf[0];
// foo.m_B.x
// CHECK-DAG: call void @llvm.dbg.value(metadata half %{{[0-9]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 96, 16)
// CHECK16-DAG: call void @llvm.dbg.value(metadata half %{{[0-9]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 48, 16)
// CHECK-DAG: call void @llvm.dbg.value(metadata half %{{[^ ,]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 96, 16)
// CHECK16-DAG: call void @llvm.dbg.value(metadata half %{{[^ ,]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 48, 16)

// foo.m_B.y
// CHECK-DAG: call void @llvm.dbg.value(metadata half %{{[0-9]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 128, 16)
// CHECK16-DAG: call void @llvm.dbg.value(metadata half %{{[0-9]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 64, 16)
// CHECK-DAG: call void @llvm.dbg.value(metadata half %{{[^ ,]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 128, 16)
// CHECK16-DAG: call void @llvm.dbg.value(metadata half %{{[^ ,]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 64, 16)

// foo.m_B.z
// CHECK-DAG: call void @llvm.dbg.value(metadata half %{{[0-9]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 160, 16)
// CHECK16-DAG: call void @llvm.dbg.value(metadata half %{{[0-9]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 80, 16)
// CHECK-DAG: call void @llvm.dbg.value(metadata half %{{[^ ,]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 160, 16)
// CHECK16-DAG: call void @llvm.dbg.value(metadata half %{{[^ ,]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 80, 16)

// foo.m_A.x
// CHECK-DAG: call void @llvm.dbg.value(metadata half %{{[0-9]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 0, 16)
// CHECK16-DAG: call void @llvm.dbg.value(metadata half %{{[0-9]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 0, 16)
// CHECK-DAG: call void @llvm.dbg.value(metadata half %{{[^ ,]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 0, 16)
// CHECK16-DAG: call void @llvm.dbg.value(metadata half %{{[^ ,]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 0, 16)

min16float value1 = foo.m_B.x;
min16float value2 = foo.m_B.y;
Expand Down
16 changes: 8 additions & 8 deletions tools/clang/test/HLSLFileCheck/dxil/debug/min16/min16int_vec.hlsl
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Original file line number Diff line number Diff line change
Expand Up @@ -16,20 +16,20 @@ void main()
{
Foo foo = buf[0];
// foo.m_B.x
// CHECK-DAG: call void @llvm.dbg.value(metadata i16 %{{[0-9]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 96, 16)
// CHECK16-DAG: call void @llvm.dbg.value(metadata i16 %{{[0-9]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 48, 16)
// CHECK-DAG: call void @llvm.dbg.value(metadata i16 %{{[^ ,]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 96, 16)
// CHECK16-DAG: call void @llvm.dbg.value(metadata i16 %{{[^ ,]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 48, 16)

// foo.m_B.y
// CHECK-DAG: call void @llvm.dbg.value(metadata i16 %{{[0-9]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 128, 16)
// CHECK16-DAG: call void @llvm.dbg.value(metadata i16 %{{[0-9]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 64, 16)
// CHECK-DAG: call void @llvm.dbg.value(metadata i16 %{{[^ ,]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 128, 16)
// CHECK16-DAG: call void @llvm.dbg.value(metadata i16 %{{[^ ,]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 64, 16)

// foo.m_B.z
// CHECK-DAG: call void @llvm.dbg.value(metadata i16 %{{[0-9]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 160, 16)
// CHECK16-DAG: call void @llvm.dbg.value(metadata i16 %{{[0-9]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 80, 16)
// CHECK-DAG: call void @llvm.dbg.value(metadata i16 %{{[^ ,]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 160, 16)
// CHECK16-DAG: call void @llvm.dbg.value(metadata i16 %{{[^ ,]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 80, 16)

// foo.m_A.x
// CHECK-DAG: call void @llvm.dbg.value(metadata i16 %{{[0-9]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 0, 16)
// CHECK16-DAG: call void @llvm.dbg.value(metadata i16 %{{[0-9]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 0, 16)
// CHECK-DAG: call void @llvm.dbg.value(metadata i16 %{{[^ ,]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 0, 16)
// CHECK16-DAG: call void @llvm.dbg.value(metadata i16 %{{[^ ,]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 0, 16)

min16int value1 = foo.m_B.x;
min16int value2 = foo.m_B.y;
Expand Down
16 changes: 8 additions & 8 deletions tools/clang/test/HLSLFileCheck/dxil/debug/min16/min16uint_vec.hlsl
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Original file line number Diff line number Diff line change
Expand Up @@ -16,20 +16,20 @@ void main()
{
Foo foo = buf[0];
// foo.m_B.x
// CHECK-DAG: call void @llvm.dbg.value(metadata i16 %{{[0-9]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 96, 16)
// CHECK16-DAG: call void @llvm.dbg.value(metadata i16 %{{[0-9]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 48, 16)
// CHECK-DAG: call void @llvm.dbg.value(metadata i16 %{{[^ ,]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 96, 16)
// CHECK16-DAG: call void @llvm.dbg.value(metadata i16 %{{[^ ,]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 48, 16)

// foo.m_B.y
// CHECK-DAG: call void @llvm.dbg.value(metadata i16 %{{[0-9]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 128, 16)
// CHECK16-DAG: call void @llvm.dbg.value(metadata i16 %{{[0-9]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 64, 16)
// CHECK-DAG: call void @llvm.dbg.value(metadata i16 %{{[^ ,]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 128, 16)
// CHECK16-DAG: call void @llvm.dbg.value(metadata i16 %{{[^ ,]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 64, 16)

// foo.m_B.z
// CHECK-DAG: call void @llvm.dbg.value(metadata i16 %{{[0-9]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 160, 16)
// CHECK16-DAG: call void @llvm.dbg.value(metadata i16 %{{[0-9]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 80, 16)
// CHECK-DAG: call void @llvm.dbg.value(metadata i16 %{{[^ ,]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 160, 16)
// CHECK16-DAG: call void @llvm.dbg.value(metadata i16 %{{[^ ,]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 80, 16)

// foo.m_A.x
// CHECK-DAG: call void @llvm.dbg.value(metadata i16 %{{[0-9]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 0, 16)
// CHECK16-DAG: call void @llvm.dbg.value(metadata i16 %{{[0-9]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 0, 16)
// CHECK-DAG: call void @llvm.dbg.value(metadata i16 %{{[^ ,]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 0, 16)
// CHECK16-DAG: call void @llvm.dbg.value(metadata i16 %{{[^ ,]+}}, i64 0, metadata !{{[0-9]+}}, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} ; var:"foo" !DIExpression(DW_OP_bit_piece, 0, 16)

min16int value1 = foo.m_B.x;
min16int value2 = foo.m_B.y;
Expand Down
36 changes: 36 additions & 0 deletions ...ng/test/HLSLFileCheck/hlsl/objects/ByteAddressBuffer/min_precision_vector_load_store.hlsl
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Original file line number Diff line number Diff line change
@@ -0,0 +1,36 @@
// RUN: %dxc -E main -T cs_6_9 %s | FileCheck %s

// Regression test for min precision rawBufferVectorLoad/Store.
// Min precision types should use i32/f32 vector operations (not i16/f16)
// to match how pre-SM6.9 RawBufferLoad handles min precision.
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Outdated

RWByteAddressBuffer g_buf : register(u0);

[numthreads(1,1,1)]
void main() {
// min16int: should load as v3i32, not v3i16
// CHECK: call %dx.types.ResRet.v3i32 @dx.op.rawBufferVectorLoad.v3i32
min16int3 vi = g_buf.Load< min16int3 >(0);
// CHECK: call void @dx.op.rawBufferVectorStore.v3i32
g_buf.Store< min16int3 >(12, vi);

// min16uint: should load as v3i32, not v3i16
// CHECK: call %dx.types.ResRet.v3i32 @dx.op.rawBufferVectorLoad.v3i32
min16uint3 vu = g_buf.Load< min16uint3 >(24);
// CHECK: call void @dx.op.rawBufferVectorStore.v3i32
g_buf.Store< min16uint3 >(36, vu);

// min16float: should load as v3f32, not v3f16
// CHECK: call %dx.types.ResRet.v3f32 @dx.op.rawBufferVectorLoad.v3f32
// CHECK: fptrunc <3 x float> {{.*}} to <3 x half>
min16float3 vf = g_buf.Load< min16float3 >(48);
// CHECK: fpext <3 x half> {{.*}} to <3 x float>
// CHECK: call void @dx.op.rawBufferVectorStore.v3f32
g_buf.Store< min16float3 >(60, vf);

// Verify i16/f16 vector ops are NOT used.
// CHECK-NOT: rawBufferVectorLoad.v{{[0-9]+}}i16
// CHECK-NOT: rawBufferVectorStore.v{{[0-9]+}}i16
// CHECK-NOT: rawBufferVectorLoad.v{{[0-9]+}}f16
// CHECK-NOT: rawBufferVectorStore.v{{[0-9]+}}f16
}
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