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75bb05e
Implement MulAdd, OutProdAcc, VecAcc lowering
anupamachandra Mar 26, 2025
913c352
Add is signed parameters to the builtins
anupamachandra Mar 26, 2025
a6863d4
Change parameter names for better readability
anupamachandra Apr 1, 2025
49bc4f0
Keeping parameter names accurate
anupamachandra Apr 1, 2025
564689a
After clang-format
anupamachandra Apr 2, 2025
6ec25f8
Fix variable names per LLVM coding standards
anupamachandra Apr 2, 2025
3081f9e
chore: autopublish 2025-04-02T15:32:45Z
github-actions[bot] Apr 2, 2025
ae115e1
Update utils/hct/hctdb.py
anupamachandra Apr 2, 2025
2b2656d
Change isSigned to isUnsigned
anupamachandra Apr 2, 2025
5ef516a
Change HLSL intrinsic args from snake to upper camel case
anupamachandra Apr 3, 2025
8c2d9ae
Name change for readability
anupamachandra Apr 3, 2025
df28777
Review Feedback: Add description for DXIL ops
anupamachandra Apr 3, 2025
a3bdc34
Fix generated files
anupamachandra Apr 3, 2025
f7fabd9
Add validation rules for DXIL ops
anupamachandra Apr 4, 2025
50155c1
Unit test 1: Check linalg builtins for different shader stages: ps, v…
anupamachandra Apr 4, 2025
9383c47
Replace std::set with linear search
anupamachandra Apr 4, 2025
8df9520
Unit test: Check Intrinsic not enabled pre SM6.9
anupamachandra Apr 4, 2025
8d44645
Unit tests: Check parameters of the Builtin calls
anupamachandra Apr 5, 2025
e70c140
Unit test: Outer Product Accumulate Multidimensional overload
anupamachandra Apr 5, 2025
6c93071
Unit test: IR->IR Dxilgen test
anupamachandra Apr 5, 2025
ee9f3a2
Unit test ; Multidim overload for MatVecMul
anupamachandra Apr 5, 2025
5d3f8b2
Simplify Matrix Layout check
anupamachandra Apr 5, 2025
d6c2806
Add checks to the HLSL source file linalg_builtins.hlsl
anupamachandra Apr 7, 2025
7d74050
Updated RUN line and renamed test
simoll Apr 7, 2025
724bebd
cleanup test
simoll Apr 8, 2025
615824d
[nfc] Fix -Werror by removing braces
simoll Apr 8, 2025
5b3b7ce
Fix debug field names for vectors > 4 elements
simoll Apr 8, 2025
453d643
[nfc] auto-format hctdb.py
simoll Apr 9, 2025
e40b24d
Move sema test to SemaHLSL test folder (spurious CodeGenHashStability…
simoll Apr 9, 2025
3d4b3ab
Merge branch 'staging-sm6.9' into anupamac/coop-vec-5
damyanp Apr 10, 2025
bc1082e
Revert SPIRV-Tools submodule to match staging-sm6.9 and main
damyanp Apr 10, 2025
5455e64
Update lib/DxilValidation/DxilValidation.cpp
simoll Apr 10, 2025
c626bdb
Update lib/DxilValidation/DxilValidation.cpp
simoll Apr 10, 2025
da9f549
Update lib/DxilValidation/DxilValidation.cpp
simoll Apr 10, 2025
ebdc454
Update lib/DxilValidation/DxilValidation.cpp
simoll Apr 10, 2025
6bb201a
Update lib/DxilValidation/DxilValidation.cpp
simoll Apr 10, 2025
3816d7c
Update lib/DxilValidation/DxilValidation.cpp
simoll Apr 10, 2025
0166d20
Update lib/DxilValidation/DxilValidation.cpp
simoll Apr 10, 2025
3027487
Update lib/DxilValidation/DxilValidation.cpp
simoll Apr 10, 2025
a80ab65
Update lib/DxilValidation/DxilValidation.cpp
simoll Apr 10, 2025
067bea3
Update lib/DxilValidation/DxilValidation.cpp
simoll Apr 10, 2025
1dc4b2d
Update lib/DxilValidation/DxilValidation.cpp
simoll Apr 10, 2025
3d06120
Update lib/DxilValidation/DxilValidation.cpp
simoll Apr 10, 2025
cde0954
Update lib/DxilValidation/DxilValidation.cpp
simoll Apr 10, 2025
372c431
[nfc] Coding Standards changes
simoll Apr 10, 2025
7633d12
Renamed params to isInput|OutputUnsigned and fixed description
simoll Apr 10, 2025
9aa5df7
Explicitly assign numbers to ComponentType enum
simoll Apr 10, 2025
d2cbc3b
Move debug info fix into separate PR #7332
simoll Apr 10, 2025
df67c9f
move all tests to CodeGenDXIL/hlsl/intrinsics/linalg_builtin and make…
simoll Apr 10, 2025
e15eacb
Move linalg-builtins.ll test to DXC/Passes/DxilGen
simoll Apr 10, 2025
9fcf8c7
Factored common code into function in check-shader-stages.hlsl
simoll Apr 10, 2025
6eb36e4
Add test variations for different matVecMul parameter settings
simoll Apr 10, 2025
e310fd6
Add test with variations for matVecMulAdd
simoll Apr 10, 2025
dff8fba
Add HLSL -> HL checks for matVecMul
simoll Apr 10, 2025
8c924ba
Add HLSL -> HL checks for matVecMulAdd
simoll Apr 10, 2025
55d8fc7
update tests to not transpose RowMajor/ColumnMajor
simoll Apr 10, 2025
5c61273
Diagnose unsigned<>type mismatches and transpose<>layout mismatch
simoll Apr 10, 2025
5b190f0
Fix merge resolution for DXIL 1.9 opcode cap.
tex3d Apr 10, 2025
b0bcab8
Update lib/DxilValidation/DxilValidation.cpp
simoll Apr 14, 2025
61607e7
Update lib/DxilValidation/DxilValidation.cpp
simoll Apr 14, 2025
78a39c6
Update lib/DxilValidation/DxilValidation.cpp
simoll Apr 14, 2025
a54d4d0
Update lib/DxilValidation/DxilValidation.cpp
simoll Apr 14, 2025
5e72dbf
Update lib/DxilValidation/DxilValidation.cpp
simoll Apr 14, 2025
50e0b73
Update lib/DxilValidation/DxilValidation.cpp
simoll Apr 14, 2025
441c4a4
Update lib/DxilValidation/DxilValidation.cpp
simoll Apr 14, 2025
083f258
Update lib/DxilValidation/DxilValidation.cpp
simoll Apr 14, 2025
ede7bdb
Update lib/DxilValidation/DxilValidation.cpp
simoll Apr 14, 2025
8675c40
Update lib/DxilValidation/DxilValidation.cpp
simoll Apr 14, 2025
82ee147
Update lib/DxilValidation/DxilValidation.cpp
simoll Apr 14, 2025
623f752
nfc: fix call after callee name change
simoll Apr 14, 2025
5d4af66
remove opcode marker
simoll Apr 14, 2025
5951621
nfc: s/\t/ /g + strip trailing wspace
simoll Apr 14, 2025
70cdd13
some more s/\t/ /g
simoll Apr 14, 2025
4d97b84
Add all params to test
simoll Apr 14, 2025
8a96622
Merge remote-tracking branch 'ms/main' into coop-vec-5
tex3d Apr 15, 2025
8ce1223
Merge remote-tracking branch 'ms/staging-sm6.9' into coop-vec-5
tex3d Apr 15, 2025
c636e6f
Update include/dxc/DXIL/DxilConstants.h
simoll Apr 15, 2025
70a83af
Update utils/hct/hctdb.py
simoll Apr 15, 2025
9cf0b99
Update utils/hct/hctdb.py
simoll Apr 15, 2025
503d4b8
Repair after DXILMatrixLayout -> LinalgMatrixLayout name change
simoll Apr 15, 2025
797d89c
Regen after attr change from 'None' -> 'ReadOnly'
simoll Apr 15, 2025
b8e4985
nfc: store output vector in tests to keep coopvec dxil ops alive
simoll Apr 15, 2025
47c4f3f
Remove redundant tests (subsumed by multioverload versions)
simoll Apr 15, 2025
cc6cc27
CheckLinalgInterpretation for InMemory and InRegister type validation
simoll Apr 15, 2025
d344e73
Align test with spec: "Note: Only Optimal layouts can be used with fo…
simoll Apr 15, 2025
faa8f8f
Align test with spec: "Packed" type conversions are bitcasts to a sma…
simoll Apr 15, 2025
41217f3
Fix DXIL OuterProductAccmulate param ordering (minterp, mlayout, mstr…
simoll Apr 15, 2025
1b23b26
Multioverload OuterProductAccmuluate test (and remove redundant
simoll Apr 15, 2025
a3f76ef
nfc: autoformat
simoll Apr 15, 2025
871694c
Merge remote-tracking branch 'ms/staging-sm6.9' into coop-vec-5
tex3d Apr 16, 2025
791dff3
Update tests with new hl opcodes
tex3d Apr 16, 2025
d5f03f2
Remvoved MatrixLayout check for OuterProductAccumulate, updated DXIL …
anupamachandra Apr 18, 2025
f5a1a51
Update linalg_builtin.hlsl to intialize input vectors for outerproduc…
anupamachandra Apr 18, 2025
1538453
Removed undefs and added named checks for resource handles in the lin…
anupamachandra Apr 18, 2025
7cbe979
Update diagnostics per llvm coding guidelines
anupamachandra Apr 18, 2025
faf6df0
Missing trailing comma was bugging darker
anupamachandra Apr 18, 2025
8782246
Fix linalg-builtins.hlsl file check: missing comma
anupamachandra Apr 18, 2025
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699 changes: 380 additions & 319 deletions docs/DXIL.rst

Large diffs are not rendered by default.

18 changes: 13 additions & 5 deletions include/dxc/DXIL/DxilConstants.h
Original file line number Diff line number Diff line change
Expand Up @@ -487,7 +487,10 @@ inline bool IsFeedbackTexture(DXIL::ResourceKind ResourceKind) {
// Enumeration for operations specified by DXIL
enum class OpCode : unsigned {
//
RawBufferVectorLoad = 303, // reads from a raw buffer and structured buffer
MatVecMul = 305, // Matrix-Vector Multiply
MatVecMulAdd = 306, // Matrix-Vector Multiply Add
OuterProductAccumulate = 307, // Outer Product Accumulate
RawBufferVectorLoad = 303, // reads from a raw buffer and structured buffer
RawBufferVectorStore =
304, // writes to a RWByteAddressBuffer or RWStructuredBuffer
Reserved0 = 226, // Reserved
Expand Down Expand Up @@ -544,6 +547,7 @@ enum class OpCode : unsigned {
ReservedC7 = 300, // reserved
ReservedC8 = 301, // reserved
ReservedC9 = 302, // reserved
VectorAccumulate = 308, // Vector Accumulate

// Amplification shader instructions
DispatchMesh = 173, // Amplification shader intrinsic DispatchMesh
Expand Down Expand Up @@ -1046,9 +1050,9 @@ enum class OpCode : unsigned {
NumOpCodes_Dxil_1_6 = 222,
NumOpCodes_Dxil_1_7 = 226,
NumOpCodes_Dxil_1_8 = 258,
NumOpCodes_Dxil_1_9 = 305,
NumOpCodes_Dxil_1_9 = 309,

NumOpCodes = 305 // exclusive last value of enumeration
NumOpCodes = 309 // exclusive last value of enumeration
};
// OPCODE-ENUM:END

Expand All @@ -1060,9 +1064,13 @@ enum class OpCode : unsigned {
// Groups for DXIL operations with equivalent function templates
enum class OpCodeClass : unsigned {
//
MatVecMul,
MatVecMulAdd,
OuterProductAccumulate,
RawBufferVectorLoad,
RawBufferVectorStore,
Reserved,
VectorAccumulate,

// Amplification shader instructions
DispatchMesh,
Expand Down Expand Up @@ -1361,9 +1369,9 @@ enum class OpCodeClass : unsigned {
NumOpClasses_Dxil_1_6 = 149,
NumOpClasses_Dxil_1_7 = 153,
NumOpClasses_Dxil_1_8 = 174,
NumOpClasses_Dxil_1_9 = 179,
NumOpClasses_Dxil_1_9 = 183,

NumOpClasses = 179 // exclusive last value of enumeration
NumOpClasses = 183 // exclusive last value of enumeration
};
// OPCODECLASS-ENUM:END

Expand Down
206 changes: 206 additions & 0 deletions include/dxc/DXIL/DxilInstructions.h
Original file line number Diff line number Diff line change
Expand Up @@ -9016,5 +9016,211 @@ struct DxilInst_RawBufferVectorStore {
llvm::APInt(32, (uint64_t)val)));
}
};

/// This instruction Matrix-Vector Multiply
struct DxilInst_MatVecMul {
llvm::Instruction *Instr;
// Construction and identification
DxilInst_MatVecMul(llvm::Instruction *pInstr) : Instr(pInstr) {}
operator bool() const {
return hlsl::OP::IsDxilOpFuncCallInst(Instr, hlsl::OP::OpCode::MatVecMul);
}
// Validation support
bool isAllowed() const { return true; }
bool isArgumentListValid() const {
if (13 != llvm::dyn_cast<llvm::CallInst>(Instr)->getNumArgOperands())
return false;
return true;
}
// Metadata
bool requiresUniformInputs() const { return false; }
// Operand indexes
enum OperandIdx {
arg_inputVector = 1,
arg_isInputSigned = 2,
arg_inputInterpretation = 3,
arg_matrixBuffer = 4,
arg_matrixOffset = 5,
arg_matrixIntepretation = 6,
arg_M = 7,
arg_K = 8,
arg_matrixLayout = 9,
arg_matrixTranspose = 10,
arg_matrixStride = 11,
arg_isOutputSigned = 12,
};
// Accessors
llvm::Value *get_inputVector() const { return Instr->getOperand(1); }
void set_inputVector(llvm::Value *val) { Instr->setOperand(1, val); }
llvm::Value *get_isInputSigned() const { return Instr->getOperand(2); }
void set_isInputSigned(llvm::Value *val) { Instr->setOperand(2, val); }
llvm::Value *get_inputInterpretation() const { return Instr->getOperand(3); }
void set_inputInterpretation(llvm::Value *val) { Instr->setOperand(3, val); }
llvm::Value *get_matrixBuffer() const { return Instr->getOperand(4); }
void set_matrixBuffer(llvm::Value *val) { Instr->setOperand(4, val); }
llvm::Value *get_matrixOffset() const { return Instr->getOperand(5); }
void set_matrixOffset(llvm::Value *val) { Instr->setOperand(5, val); }
llvm::Value *get_matrixIntepretation() const { return Instr->getOperand(6); }
void set_matrixIntepretation(llvm::Value *val) { Instr->setOperand(6, val); }
llvm::Value *get_M() const { return Instr->getOperand(7); }
void set_M(llvm::Value *val) { Instr->setOperand(7, val); }
llvm::Value *get_K() const { return Instr->getOperand(8); }
void set_K(llvm::Value *val) { Instr->setOperand(8, val); }
llvm::Value *get_matrixLayout() const { return Instr->getOperand(9); }
void set_matrixLayout(llvm::Value *val) { Instr->setOperand(9, val); }
llvm::Value *get_matrixTranspose() const { return Instr->getOperand(10); }
void set_matrixTranspose(llvm::Value *val) { Instr->setOperand(10, val); }
llvm::Value *get_matrixStride() const { return Instr->getOperand(11); }
void set_matrixStride(llvm::Value *val) { Instr->setOperand(11, val); }
llvm::Value *get_isOutputSigned() const { return Instr->getOperand(12); }
void set_isOutputSigned(llvm::Value *val) { Instr->setOperand(12, val); }
};

/// This instruction Matrix-Vector Multiply Add
struct DxilInst_MatVecMulAdd {
llvm::Instruction *Instr;
// Construction and identification
DxilInst_MatVecMulAdd(llvm::Instruction *pInstr) : Instr(pInstr) {}
operator bool() const {
return hlsl::OP::IsDxilOpFuncCallInst(Instr,
hlsl::OP::OpCode::MatVecMulAdd);
}
// Validation support
bool isAllowed() const { return true; }
bool isArgumentListValid() const {
if (16 != llvm::dyn_cast<llvm::CallInst>(Instr)->getNumArgOperands())
return false;
return true;
}
// Metadata
bool requiresUniformInputs() const { return false; }
// Operand indexes
enum OperandIdx {
arg_inputVector = 1,
arg_isInputSigned = 2,
arg_inputInterpretation = 3,
arg_matrixBuffer = 4,
arg_matrixOffset = 5,
arg_matrixIntepretation = 6,
arg_M = 7,
arg_K = 8,
arg_matrixLayout = 9,
arg_matrixTranspose = 10,
arg_matrixStride = 11,
arg_biasBuffer = 12,
arg_biasOffset = 13,
arg_biasIntepretation = 14,
arg_isOutputSigned = 15,
};
// Accessors
llvm::Value *get_inputVector() const { return Instr->getOperand(1); }
void set_inputVector(llvm::Value *val) { Instr->setOperand(1, val); }
llvm::Value *get_isInputSigned() const { return Instr->getOperand(2); }
void set_isInputSigned(llvm::Value *val) { Instr->setOperand(2, val); }
llvm::Value *get_inputInterpretation() const { return Instr->getOperand(3); }
void set_inputInterpretation(llvm::Value *val) { Instr->setOperand(3, val); }
llvm::Value *get_matrixBuffer() const { return Instr->getOperand(4); }
void set_matrixBuffer(llvm::Value *val) { Instr->setOperand(4, val); }
llvm::Value *get_matrixOffset() const { return Instr->getOperand(5); }
void set_matrixOffset(llvm::Value *val) { Instr->setOperand(5, val); }
llvm::Value *get_matrixIntepretation() const { return Instr->getOperand(6); }
void set_matrixIntepretation(llvm::Value *val) { Instr->setOperand(6, val); }
llvm::Value *get_M() const { return Instr->getOperand(7); }
void set_M(llvm::Value *val) { Instr->setOperand(7, val); }
llvm::Value *get_K() const { return Instr->getOperand(8); }
void set_K(llvm::Value *val) { Instr->setOperand(8, val); }
llvm::Value *get_matrixLayout() const { return Instr->getOperand(9); }
void set_matrixLayout(llvm::Value *val) { Instr->setOperand(9, val); }
llvm::Value *get_matrixTranspose() const { return Instr->getOperand(10); }
void set_matrixTranspose(llvm::Value *val) { Instr->setOperand(10, val); }
llvm::Value *get_matrixStride() const { return Instr->getOperand(11); }
void set_matrixStride(llvm::Value *val) { Instr->setOperand(11, val); }
llvm::Value *get_biasBuffer() const { return Instr->getOperand(12); }
void set_biasBuffer(llvm::Value *val) { Instr->setOperand(12, val); }
llvm::Value *get_biasOffset() const { return Instr->getOperand(13); }
void set_biasOffset(llvm::Value *val) { Instr->setOperand(13, val); }
llvm::Value *get_biasIntepretation() const { return Instr->getOperand(14); }
void set_biasIntepretation(llvm::Value *val) { Instr->setOperand(14, val); }
llvm::Value *get_isOutputSigned() const { return Instr->getOperand(15); }
void set_isOutputSigned(llvm::Value *val) { Instr->setOperand(15, val); }
};

/// This instruction Outer Product Accumulate
struct DxilInst_OuterProductAccumulate {
llvm::Instruction *Instr;
// Construction and identification
DxilInst_OuterProductAccumulate(llvm::Instruction *pInstr) : Instr(pInstr) {}
operator bool() const {
return hlsl::OP::IsDxilOpFuncCallInst(
Instr, hlsl::OP::OpCode::OuterProductAccumulate);
}
// Validation support
bool isAllowed() const { return true; }
bool isArgumentListValid() const {
if (8 != llvm::dyn_cast<llvm::CallInst>(Instr)->getNumArgOperands())
return false;
return true;
}
// Metadata
bool requiresUniformInputs() const { return false; }
// Operand indexes
enum OperandIdx {
arg_inputVector1 = 1,
arg_inputVector2 = 2,
arg_matrixBuffer = 3,
arg_matrixOffset = 4,
arg_matrixStride = 5,
arg_matrixIntepretation = 6,
arg_matrixLayout = 7,
};
// Accessors
llvm::Value *get_inputVector1() const { return Instr->getOperand(1); }
void set_inputVector1(llvm::Value *val) { Instr->setOperand(1, val); }
llvm::Value *get_inputVector2() const { return Instr->getOperand(2); }
void set_inputVector2(llvm::Value *val) { Instr->setOperand(2, val); }
llvm::Value *get_matrixBuffer() const { return Instr->getOperand(3); }
void set_matrixBuffer(llvm::Value *val) { Instr->setOperand(3, val); }
llvm::Value *get_matrixOffset() const { return Instr->getOperand(4); }
void set_matrixOffset(llvm::Value *val) { Instr->setOperand(4, val); }
llvm::Value *get_matrixStride() const { return Instr->getOperand(5); }
void set_matrixStride(llvm::Value *val) { Instr->setOperand(5, val); }
llvm::Value *get_matrixIntepretation() const { return Instr->getOperand(6); }
void set_matrixIntepretation(llvm::Value *val) { Instr->setOperand(6, val); }
llvm::Value *get_matrixLayout() const { return Instr->getOperand(7); }
void set_matrixLayout(llvm::Value *val) { Instr->setOperand(7, val); }
};

/// This instruction Vector Accumulate
struct DxilInst_VectorAccumulate {
llvm::Instruction *Instr;
// Construction and identification
DxilInst_VectorAccumulate(llvm::Instruction *pInstr) : Instr(pInstr) {}
operator bool() const {
return hlsl::OP::IsDxilOpFuncCallInst(Instr,
hlsl::OP::OpCode::VectorAccumulate);
}
// Validation support
bool isAllowed() const { return true; }
bool isArgumentListValid() const {
if (4 != llvm::dyn_cast<llvm::CallInst>(Instr)->getNumArgOperands())
return false;
return true;
}
// Metadata
bool requiresUniformInputs() const { return false; }
// Operand indexes
enum OperandIdx {
arg_inputVector = 1,
arg_arrayBuffer = 2,
arg_arrayOffset = 3,
};
// Accessors
llvm::Value *get_inputVector() const { return Instr->getOperand(1); }
void set_inputVector(llvm::Value *val) { Instr->setOperand(1, val); }
llvm::Value *get_arrayBuffer() const { return Instr->getOperand(2); }
void set_arrayBuffer(llvm::Value *val) { Instr->setOperand(2, val); }
llvm::Value *get_arrayOffset() const { return Instr->getOperand(3); }
void set_arrayOffset(llvm::Value *val) { Instr->setOperand(3, val); }
};
// INSTR-HELPER:END
} // namespace hlsl
48 changes: 48 additions & 0 deletions include/dxc/HLSL/HLOperations.h
Original file line number Diff line number Diff line change
Expand Up @@ -433,6 +433,54 @@ const unsigned kNodeHandleToResCastOpIdx = 1;
const unsigned kAnnotateNodeHandleNodePropIdx = 2;
const unsigned kAnnotateNodeRecordHandleNodeRecordPropIdx = 2;

// Linear Algebra Operations

// MatVecMul
const unsigned kMatVecMulOutputVectorIdx = 1;
const unsigned kMatVecMulIsOutputUnsignedIdx = 2;
const unsigned kMatVecMulInputVectorIdx = 3;
const unsigned kMatVecMulIsInputUnsignedIdx = 4;
const unsigned kMatVecMulInputInterpretationIdx = 5;
const unsigned kMatVecMulMatrixBufferIdx = 6;
const unsigned kMatVecMulMatrixOffsetIdx = 7;
const unsigned kMatVecMulMatrixInterpretationIdx = 8;
const unsigned kMatVecMulMatrixMIdx = 9;
const unsigned kMatVecMulMatrixKIdx = 10;
const unsigned kMatVecMulMatrixLayoutIdx = 11;
const unsigned kMatVecMulMatrixTransposeIdx = 12;
const unsigned kMatVecMulMatrixStrideIdx = 13;

// MatVecMulAdd
const unsigned kMatVecMulAddOutputVectorIdx = 1;
const unsigned kMatVecMulAddIsOutputUnsignedIdx = 2;
const unsigned kMatVecMulAddInputVectorIdx = 3;
const unsigned kMatVecMulAddIsInputUnsignedIdx = 4;
const unsigned kMatVecMulAddInputInterpretationIdx = 5;
const unsigned kMatVecMulAddMatrixBufferIdx = 6;
const unsigned kMatVecMulAddMatrixOffsetIdx = 7;
const unsigned kMatVecMulAddMatrixInterpretationIdx = 8;
const unsigned kMatVecMulAddMatrixMIdx = 9;
const unsigned kMatVecMulAddMatrixKIdx = 10;
const unsigned kMatVecMulAddMatrixLayoutIdx = 11;
const unsigned kMatVecMulAddMatrixTransposeIdx = 12;
const unsigned kMatVecMulAddMatrixStrideIdx = 13;
const unsigned kMatVecMulAddBiasBufferIdx = 14;
const unsigned kMatVecMulAddBiasOffsetIdx = 15;
const unsigned kMatVecMulAddBiasInterpretationIdx = 16;

// OuterProductAccumulate
const unsigned kOuterProdAccInputVec1Idx = 1;
const unsigned kOuterProdAccInputVec2Idx = 2;
const unsigned kOuterProdAccMatrixIdx = 3;
const unsigned kOuterProdAccMatrixOffsetIdx = 4;
const unsigned kOuterProdAccMatrixInterpretationIdx = 5;
const unsigned kOuterProdAccMatrixLayoutIdx = 6;
const unsigned kOuterProdAccMatrixStrideIdx = 7;

// Vector Accumulate
const unsigned kVectorAccInputVecIdx = 1;
const unsigned kVectorAccMatrixIdx = 2;
const unsigned kVectorAccMatrixOffsetIdx = 3;
} // namespace HLOperandIndex

llvm::Function *GetOrCreateHLFunction(llvm::Module &M,
Expand Down
10 changes: 7 additions & 3 deletions include/dxc/HlslIntrinsicOp.h
Original file line number Diff line number Diff line change
Expand Up @@ -333,8 +333,6 @@ enum class IntrinsicOp {
MOP_TraceRayInline = 325,
MOP_WorldRayDirection = 326,
MOP_WorldRayOrigin = 327,
MOP_DxHitObject_MakeNop = 358,
IOP_DxMaybeReorderThread = 359,
MOP_Count = 328,
MOP_FinishedCrossGroupSharing = 329,
MOP_GetGroupNodeOutputRecords = 330,
Expand Down Expand Up @@ -366,7 +364,13 @@ enum class IntrinsicOp {
IOP_usign = 355,
MOP_InterlockedUMax = 356,
MOP_InterlockedUMin = 357,
Num_Intrinsics = 360,
MOP_DxHitObject_MakeNop = 358,
IOP_DxMaybeReorderThread = 359,
IOP___builtin_MatVecMul = 360,
IOP___builtin_MatVecMulAdd = 361,
IOP___builtin_OuterProductAccumulate = 362,
IOP___builtin_VectorAccumulate = 363,
Num_Intrinsics = 364,
};
inline bool HasUnsignedIntrinsicOpcode(IntrinsicOp opcode) {
switch (opcode) {
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