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AnsuelLinus Walleij
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pinctrl: airoha: fix wrong MDIO function bitmaks
With further testing with an attached Aeonsemi it was discovered that the pinctrl MDIO function applied the wrong bitmask. The error was probably caused by the confusing documentation related to these bits. Inspecting what the bootloader actually configure, the SGMII_MDIO_MODE is never actually set but instead it's set force enable to the 2 GPIO (gpio 1-2) for MDC and MDIO pin. The usage of GPIO might be confusing but this is just to instruct the SoC to not mess with those 2 PIN and as Benjamin reported it's also an Errata of 7581. The FORCE_GPIO_EN doesn't set them as GPIO function (that is configured by a different register) but it's really to actually ""enable"" those lines. Normally the SoC should autodetect this by HW but it seems AN7581 have problem with this and require this workaround to force enable the 2 pin. Applying this configuration permits correct functionality of any externally attached PHY. Cc: [email protected] Fixes: 1c8ace2 ("pinctrl: airoha: Add support for EN7581 SoC") Signed-off-by: Christian Marangi <[email protected]> Acked-by: Benjamin Larsson <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
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Lines changed: 9 additions & 6 deletions

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drivers/pinctrl/mediatek/pinctrl-airoha.c

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -108,6 +108,9 @@
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#define JTAG_UDI_EN_MASK BIT(4)
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#define JTAG_DFD_EN_MASK BIT(3)
110110

111+
#define REG_FORCE_GPIO_EN 0x0228
112+
#define FORCE_GPIO_EN(n) BIT(n)
113+
111114
/* LED MAP */
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#define REG_LAN_LED0_MAPPING 0x027c
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#define REG_LAN_LED1_MAPPING 0x0280
@@ -718,17 +721,17 @@ static const struct airoha_pinctrl_func_group mdio_func_group[] = {
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{
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.name = "mdio",
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.regmap[0] = {
721-
AIROHA_FUNC_MUX,
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REG_GPIO_PON_MODE,
723-
GPIO_SGMII_MDIO_MODE_MASK,
724-
GPIO_SGMII_MDIO_MODE_MASK
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},
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.regmap[1] = {
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AIROHA_FUNC_MUX,
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REG_GPIO_2ND_I2C_MODE,
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GPIO_MDC_IO_MASTER_MODE_MODE,
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GPIO_MDC_IO_MASTER_MODE_MODE
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},
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.regmap[1] = {
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AIROHA_FUNC_MUX,
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REG_FORCE_GPIO_EN,
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FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2),
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FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2)
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},
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.regmap_size = 2,
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},
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};

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