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prabhakarladgeertu
prabhakarlad
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geertu
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clk: renesas: r9a09g057: Add entries for RSCIs
Add clock and reset entries for the RSCI IPs. Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
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‎drivers/clk/renesas/r9a09g057-cpg.c‎

Lines changed: 126 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,9 @@ enum clk_ids {
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CLK_PLLCLN_DIV2,
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CLK_PLLCLN_DIV8,
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CLK_PLLCLN_DIV16,
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CLK_PLLCLN_DIV64,
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CLK_PLLCLN_DIV256,
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CLK_PLLCLN_DIV1024,
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CLK_PLLDTY_ACPU,
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CLK_PLLDTY_ACPU_DIV2,
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CLK_PLLDTY_ACPU_DIV4,
@@ -182,6 +185,9 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
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DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
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DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
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DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
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DEF_FIXED(".pllcln_div64", CLK_PLLCLN_DIV64, CLK_PLLCLN, 1, 64),
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DEF_FIXED(".pllcln_div256", CLK_PLLCLN_DIV256, CLK_PLLCLN, 1, 256),
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DEF_FIXED(".pllcln_div1024", CLK_PLLCLN_DIV1024, CLK_PLLCLN, 1, 1024),
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DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
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DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
@@ -288,6 +294,106 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
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BUS_MSTOP(5, BIT(13))),
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DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
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BUS_MSTOP(5, BIT(13))),
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DEF_MOD("rsci0_pclk", CLK_PLLCLN_DIV16, 5, 13, 2, 29,
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BUS_MSTOP(11, BIT(3))),
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DEF_MOD("rsci0_tclk", CLK_PLLCLN_DIV16, 5, 14, 2, 30,
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BUS_MSTOP(11, BIT(3))),
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DEF_MOD("rsci0_ps_ps3_n", CLK_PLLCLN_DIV1024, 5, 15, 2, 31,
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BUS_MSTOP(11, BIT(3))),
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DEF_MOD("rsci0_ps_ps2_n", CLK_PLLCLN_DIV256, 6, 0, 3, 0,
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BUS_MSTOP(11, BIT(3))),
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DEF_MOD("rsci0_ps_ps1_n", CLK_PLLCLN_DIV64, 6, 1, 3, 1,
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BUS_MSTOP(11, BIT(3))),
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DEF_MOD("rsci1_pclk", CLK_PLLCLN_DIV16, 6, 2, 3, 2,
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BUS_MSTOP(11, BIT(4))),
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DEF_MOD("rsci1_tclk", CLK_PLLCLN_DIV16, 6, 3, 3, 3,
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BUS_MSTOP(11, BIT(4))),
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DEF_MOD("rsci1_ps_ps3_n", CLK_PLLCLN_DIV1024, 6, 4, 3, 4,
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BUS_MSTOP(11, BIT(4))),
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DEF_MOD("rsci1_ps_ps2_n", CLK_PLLCLN_DIV256, 6, 5, 3, 5,
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BUS_MSTOP(11, BIT(4))),
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DEF_MOD("rsci1_ps_ps1_n", CLK_PLLCLN_DIV64, 6, 6, 3, 6,
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BUS_MSTOP(11, BIT(4))),
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DEF_MOD("rsci2_pclk", CLK_PLLCLN_DIV16, 6, 7, 3, 7,
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BUS_MSTOP(11, BIT(5))),
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DEF_MOD("rsci2_tclk", CLK_PLLCLN_DIV16, 6, 8, 3, 8,
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BUS_MSTOP(11, BIT(5))),
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DEF_MOD("rsci2_ps_ps3_n", CLK_PLLCLN_DIV1024, 6, 9, 3, 9,
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BUS_MSTOP(11, BIT(5))),
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DEF_MOD("rsci2_ps_ps2_n", CLK_PLLCLN_DIV256, 6, 10, 3, 10,
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BUS_MSTOP(11, BIT(5))),
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DEF_MOD("rsci2_ps_ps1_n", CLK_PLLCLN_DIV64, 6, 11, 3, 11,
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BUS_MSTOP(11, BIT(5))),
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DEF_MOD("rsci3_pclk", CLK_PLLCLN_DIV16, 6, 12, 3, 12,
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BUS_MSTOP(11, BIT(6))),
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DEF_MOD("rsci3_tclk", CLK_PLLCLN_DIV16, 6, 13, 3, 13,
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BUS_MSTOP(11, BIT(6))),
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DEF_MOD("rsci3_ps_ps3_n", CLK_PLLCLN_DIV1024, 6, 14, 3, 14,
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BUS_MSTOP(11, BIT(6))),
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DEF_MOD("rsci3_ps_ps2_n", CLK_PLLCLN_DIV256, 6, 15, 3, 15,
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BUS_MSTOP(11, BIT(6))),
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DEF_MOD("rsci3_ps_ps1_n", CLK_PLLCLN_DIV64, 7, 0, 3, 16,
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BUS_MSTOP(11, BIT(6))),
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DEF_MOD("rsci4_pclk", CLK_PLLCLN_DIV16, 7, 1, 3, 17,
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BUS_MSTOP(11, BIT(7))),
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DEF_MOD("rsci4_tclk", CLK_PLLCLN_DIV16, 7, 2, 3, 18,
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BUS_MSTOP(11, BIT(7))),
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DEF_MOD("rsci4_ps_ps3_n", CLK_PLLCLN_DIV1024, 7, 3, 3, 19,
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BUS_MSTOP(11, BIT(7))),
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DEF_MOD("rsci4_ps_ps2_n", CLK_PLLCLN_DIV256, 7, 4, 3, 20,
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BUS_MSTOP(11, BIT(7))),
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DEF_MOD("rsci4_ps_ps1_n", CLK_PLLCLN_DIV64, 7, 5, 3, 21,
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BUS_MSTOP(11, BIT(7))),
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DEF_MOD("rsci5_pclk", CLK_PLLCLN_DIV16, 7, 6, 3, 22,
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BUS_MSTOP(11, BIT(8))),
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DEF_MOD("rsci5_tclk", CLK_PLLCLN_DIV16, 7, 7, 3, 23,
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BUS_MSTOP(11, BIT(8))),
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DEF_MOD("rsci5_ps_ps3_n", CLK_PLLCLN_DIV1024, 7, 8, 3, 24,
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BUS_MSTOP(11, BIT(8))),
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DEF_MOD("rsci5_ps_ps2_n", CLK_PLLCLN_DIV256, 7, 9, 3, 25,
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BUS_MSTOP(11, BIT(8))),
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DEF_MOD("rsci5_ps_ps1_n", CLK_PLLCLN_DIV64, 7, 10, 3, 26,
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BUS_MSTOP(11, BIT(8))),
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DEF_MOD("rsci6_pclk", CLK_PLLCLN_DIV16, 7, 11, 3, 27,
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BUS_MSTOP(11, BIT(9))),
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DEF_MOD("rsci6_tclk", CLK_PLLCLN_DIV16, 7, 12, 3, 28,
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BUS_MSTOP(11, BIT(9))),
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DEF_MOD("rsci6_ps_ps3_n", CLK_PLLCLN_DIV1024, 7, 13, 3, 29,
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BUS_MSTOP(11, BIT(9))),
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DEF_MOD("rsci6_ps_ps2_n", CLK_PLLCLN_DIV256, 7, 14, 3, 30,
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BUS_MSTOP(11, BIT(9))),
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DEF_MOD("rsci6_ps_ps1_n", CLK_PLLCLN_DIV64, 7, 15, 3, 31,
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BUS_MSTOP(11, BIT(9))),
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DEF_MOD("rsci7_pclk", CLK_PLLCLN_DIV16, 8, 0, 4, 0,
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BUS_MSTOP(11, BIT(10))),
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DEF_MOD("rsci7_tclk", CLK_PLLCLN_DIV16, 8, 1, 4, 1,
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BUS_MSTOP(11, BIT(10))),
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DEF_MOD("rsci7_ps_ps3_n", CLK_PLLCLN_DIV1024, 8, 2, 4, 2,
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BUS_MSTOP(11, BIT(10))),
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DEF_MOD("rsci7_ps_ps2_n", CLK_PLLCLN_DIV256, 8, 3, 4, 3,
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BUS_MSTOP(11, BIT(10))),
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DEF_MOD("rsci7_ps_ps1_n", CLK_PLLCLN_DIV64, 8, 4, 4, 4,
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BUS_MSTOP(11, BIT(10))),
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DEF_MOD("rsci8_pclk", CLK_PLLCLN_DIV16, 8, 5, 4, 5,
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BUS_MSTOP(11, BIT(11))),
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DEF_MOD("rsci8_tclk", CLK_PLLCLN_DIV16, 8, 6, 4, 6,
380+
BUS_MSTOP(11, BIT(11))),
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DEF_MOD("rsci8_ps_ps3_n", CLK_PLLCLN_DIV1024, 8, 7, 4, 7,
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BUS_MSTOP(11, BIT(11))),
383+
DEF_MOD("rsci8_ps_ps2_n", CLK_PLLCLN_DIV256, 8, 8, 4, 8,
384+
BUS_MSTOP(11, BIT(11))),
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DEF_MOD("rsci8_ps_ps1_n", CLK_PLLCLN_DIV64, 8, 9, 4, 9,
386+
BUS_MSTOP(11, BIT(11))),
387+
DEF_MOD("rsci9_pclk", CLK_PLLCLN_DIV16, 8, 10, 4, 10,
388+
BUS_MSTOP(11, BIT(12))),
389+
DEF_MOD("rsci9_tclk", CLK_PLLCLN_DIV16, 8, 11, 4, 11,
390+
BUS_MSTOP(11, BIT(12))),
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DEF_MOD("rsci9_ps_ps3_n", CLK_PLLCLN_DIV1024, 8, 12, 4, 12,
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BUS_MSTOP(11, BIT(12))),
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DEF_MOD("rsci9_ps_ps2_n", CLK_PLLCLN_DIV256, 8, 13, 4, 13,
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BUS_MSTOP(11, BIT(12))),
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DEF_MOD("rsci9_ps_ps1_n", CLK_PLLCLN_DIV64, 8, 14, 4, 14,
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BUS_MSTOP(11, BIT(12))),
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DEF_MOD("rtc_0_clk_rtc", CLK_PLLCM33_DIV16, 5, 3, 2, 19,
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BUS_MSTOP(3, BIT(11) | BIT(12))),
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DEF_MOD("rspi_0_pclk", CLK_PLLCLN_DIV8, 5, 4, 2, 20,
@@ -488,6 +594,26 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
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DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
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DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
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DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
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DEF_RST(8, 1, 3, 18), /* RSCI0_PRESETN */
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DEF_RST(8, 2, 3, 19), /* RSCI0_TRESETN */
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DEF_RST(8, 3, 3, 20), /* RSCI1_PRESETN */
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DEF_RST(8, 4, 3, 21), /* RSCI1_TRESETN */
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DEF_RST(8, 5, 3, 22), /* RSCI2_PRESETN */
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DEF_RST(8, 6, 3, 23), /* RSCI2_TRESETN */
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DEF_RST(8, 7, 3, 24), /* RSCI3_PRESETN */
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DEF_RST(8, 8, 3, 25), /* RSCI3_TRESETN */
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DEF_RST(8, 9, 3, 26), /* RSCI4_PRESETN */
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DEF_RST(8, 10, 3, 27), /* RSCI4_TRESETN */
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DEF_RST(8, 11, 3, 28), /* RSCI5_PRESETN */
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DEF_RST(8, 12, 3, 29), /* RSCI5_TRESETN */
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DEF_RST(8, 13, 3, 30), /* RSCI6_PRESETN */
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DEF_RST(8, 14, 3, 31), /* RSCI6_TRESETN */
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DEF_RST(8, 15, 4, 0), /* RSCI7_PRESETN */
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DEF_RST(9, 0, 4, 1), /* RSCI7_TRESETN */
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DEF_RST(9, 1, 4, 2), /* RSCI8_PRESETN */
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DEF_RST(9, 2, 4, 3), /* RSCI8_TRESETN */
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DEF_RST(9, 3, 4, 4), /* RSCI9_PRESETN */
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DEF_RST(9, 4, 4, 5), /* RSCI9_TRESETN */
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DEF_RST(7, 9, 3, 10), /* RTC_0_RST_RTC */
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DEF_RST(7, 10, 3, 11), /* RTC_0_RST_RTC_V */
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DEF_RST(7, 11, 3, 12), /* RSPI_0_PRESETN */

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