Hello,
I've identified a critical inconsistency between the SignalSDRPro schematic and HDL constraints
https://github.com/signalens/hdl/blob/3bccc10b1488e323fb27ebe771b35ed076e14c3b/projects/signalsdrpro/system_constr.xdc
https://github.com/signalens/signalsdrpro/blob/main/diagram/SignalSDRPro%20Logic%20diagrams.pdf
Problem Details
Schematic shows:
- AD9361's TXNRX pin (H4) is connected to VCC1V8_IF
- Zynq FPGA's P14 is connected to I2C-SDA (associated with two EEPROMs)
- HDL constraints define:
- FPGA pin P14 is assigned to AD9361's H4 (TXNRX)
set_property PACKAGE_PIN p14 [get_ports txnrx]
These contradictory connections create a design conflict that needs to be resolved.
Expected Behavior
Based on industry standard designs (Pluto SDR and USRP B210), the TXNRX signal from the AD9361 should be directly connected to the FPGA, with the schematic and HDL constraints in agreement.
Questions
- Is this an error in the schematic or in the HDL constraints?
- What is the intended function of the two EEPROMs connected to I2C-SDA?
Hello,
I've identified a critical inconsistency between the SignalSDRPro schematic and HDL constraints
https://github.com/signalens/hdl/blob/3bccc10b1488e323fb27ebe771b35ed076e14c3b/projects/signalsdrpro/system_constr.xdc
https://github.com/signalens/signalsdrpro/blob/main/diagram/SignalSDRPro%20Logic%20diagrams.pdf
Problem Details
Schematic shows:
set_property PACKAGE_PIN p14 [get_ports txnrx]These contradictory connections create a design conflict that needs to be resolved.
Expected Behavior
Based on industry standard designs (Pluto SDR and USRP B210), the TXNRX signal from the AD9361 should be directly connected to the FPGA, with the schematic and HDL constraints in agreement.
Questions