Add landing pad instructions for IBT (amd64) and BTI (arm64)#81
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VlkrS wants to merge 4 commits into
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Thank you for the contribution! At the very least this change would need CI to be set up such that these absence of these changes would result in a failure (ignoring all those other tests failing for unrelated reasons) |
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That's tricky in so far as the CI environment would need to be capable of BTI/IBT and it would need to run with an OS that enforces it... |
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Would QEMU be able to emulate these capabilities? EDIT: sorry for a late reply, your response fell through the cracks in my notifications. |
Author
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I don't think QEMU can emulate these capabilities, but the referenced docs clearly state that the worst that can happen is that you're adding NOPs. |
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Applications using psm on systems which enforce Indirect Branch Tracking [1] on amd64 or Branch Target Identification [2] on arm64 currently crash.
This PR adds the necessary landing pad instructions for both platforms.
[1] https://edc.intel.com/content/www/us/en/design/ipla/software-development-platforms/client/platforms/alder-lake-desktop/12th-generation-intel-core-processors-datasheet-volume-1-of-2/indirect-branch-tracking/
[2] https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/BTI--Branch-Target-Identification-