diff --git a/src/hotspot/cpu/aarch64/vmStructs_aarch64.hpp b/src/hotspot/cpu/aarch64/vmStructs_aarch64.hpp index a9f2d2ff2aa..2ec901f6a2e 100644 --- a/src/hotspot/cpu/aarch64/vmStructs_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/vmStructs_aarch64.hpp @@ -41,7 +41,7 @@ #define VM_LONG_CONSTANTS_CPU(declare_constant, declare_preprocessor_constant) -#define DECLARE_INT_CPU_FEATURE_CONSTANT(id, name) GENERATE_VM_INT_CONSTANT_ENTRY(VM_Version::CPU_##id) +#define DECLARE_INT_CPU_FEATURE_CONSTANT(id, name, bit) GENERATE_VM_INT_CONSTANT_ENTRY(VM_Version::CPU_##id) #define VM_INT_CPU_FEATURE_CONSTANTS CPU_FEATURE_FLAGS(DECLARE_INT_CPU_FEATURE_CONSTANT) #endif // CPU_AARCH64_VMSTRUCTS_AARCH64_HPP diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp index 0aa701a2bd6..5082770291d 100644 --- a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp @@ -59,8 +59,6 @@ GLIBC_UNSUPPORTED(SVEBITPERM); \ GLIBC_UNSUPPORTED(SVE2 ); \ GLIBC_UNSUPPORTED(A53MAC ); \ - GLIBC_UNSUPPORTED(ECV ); \ - GLIBC_UNSUPPORTED(WFXT ); \ GLIBC_UNSUPPORTED(NOTPACA ); \ /**/ #include "runtime/abstract_vm_version.inline.hpp" @@ -89,7 +87,7 @@ bool VM_Version::_ic_ivau_trapped; VM_Version::VM_Features VM_Version::_features; VM_Version::VM_Features VM_Version::_cpu_features; -#define DECLARE_CPU_FEATURE_NAME(id, name) XSTR(name), +#define DECLARE_CPU_FEATURE_NAME(id, name, bit) XSTR(name), const char* VM_Version::_features_names[] = { CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_NAME)}; #undef DECLARE_CPU_FEATURE_NAME @@ -888,17 +886,9 @@ bool VM_Version::cpu_features_binary(VM_Version::VM_Features *data) { } VM_Features VM_Version::CPUFeatures_generic() { - VM_Features retval; - retval.set_feature(CPU_FP); - retval.set_feature(CPU_ASIMD); - // PACA cannot be made compatible between CPUs that do and do not support it. - if (_cpu_features.supports_feature(CPU_PACA)) { - retval.set_feature(CPU_PACA); - } - if (_cpu_features.supports_feature(CPU_NOTPACA)) { - retval.set_feature(CPU_NOTPACA); - } - return retval; + // CPU_PACA and non-PACA processors cannot share the same image. Also we cannot disable glibc using features like CPU_LSE. + vm_exit_during_initialization("-XX:CPUFeatures=generic is not available on aarch64"); + ShouldNotReachHere(); } void VM_Version::print_using_features_cr() { diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp index b353d7a3560..f6f2977cce1 100644 --- a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp @@ -34,37 +34,39 @@ class VM_Feature_Flag { public: -#define CPU_FEATURE_FLAGS(decl) \ - decl(FP, fp ) \ - decl(ASIMD, asimd ) \ - decl(EVTSTRM, evtstrm ) \ - decl(AES, aes ) \ - decl(PMULL, pmull ) \ - decl(SHA1, sha1 ) \ - decl(SHA2, sha256 ) \ - decl(CRC32, crc32 ) \ - decl(LSE, lse ) \ - decl(FPHP, fphp ) \ - decl(ASIMDHP, asimdhp ) \ - decl(DCPOP, dcpop ) \ - decl(SHA3, sha3 ) \ - decl(SHA512, sha512 ) \ - decl(SVE, sve ) \ - decl(SB, sb ) \ - decl(PACA, paca ) \ - decl(SVEBITPERM, svebitperm) \ - decl(SVE2, sve2 ) \ - decl(A53MAC, a53mac ) \ - decl(ECV, ecv ) \ - decl(WFXT, wfxt ) \ - decl(NOTPACA, notpaca ) \ +#define CPU_FEATURE_FLAGS(decl) \ + decl(FP, fp, 0) \ + decl(ASIMD, asimd, 1) \ + decl(EVTSTRM, evtstrm, 2) \ + decl(AES, aes, 3) \ + decl(PMULL, pmull, 4) \ + decl(SHA1, sha1, 5) \ + decl(SHA2, sha256, 6) \ + decl(CRC32, crc32, 7) \ + decl(LSE, lse, 8) \ + decl(FPHP, fphp, 9) \ + decl(ASIMDHP, asimdhp, 10) \ + decl(DCPOP, dcpop, 11) \ + decl(SHA3, sha3, 12) \ + decl(SHA512, sha512, 13) \ + decl(SVE, sve, 14) \ + decl(SB, sb, 15) \ + decl(PACA, paca, 16) \ + decl(SVEBITPERM, svebitperm, 17) \ + decl(SVE2, sve2, 18) \ + decl(A53MAC, a53mac, 19) \ + decl(ECV, ecv, 20) \ + decl(WFXT, wfxt, 21) \ + /* These features are added for CRaC. */ \ + decl(NOTPACA, notpaca, 63) \ /**/ enum Feature_Flag { - #define DECLARE_CPU_FEATURE_FLAG(id, name) CPU_##id, + #define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (bit), CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG) #undef DECLARE_CPU_FEATURE_FLAG - MAX_CPU_FEATURES + MAX_CPU_FEATURES, + FIRST_GLIBC_FEATURE = CPU_NOTPACA }; }; @@ -215,7 +217,7 @@ class VM_Version : public Abstract_VM_Version, public VM_Feature_Flag { static const char* _features_names[]; // Feature identification -#define CPU_FEATURE_DETECTION(id, name) \ +#define CPU_FEATURE_DETECTION(id, name, bit) \ static bool supports_##name() { return supports_feature(CPU_##id); } CPU_FEATURE_FLAGS(CPU_FEATURE_DETECTION) #undef CPU_FEATURE_DETECTION diff --git a/src/hotspot/cpu/x86/vmStructs_x86.hpp b/src/hotspot/cpu/x86/vmStructs_x86.hpp index e0fcc7d375a..b8089a6413e 100644 --- a/src/hotspot/cpu/x86/vmStructs_x86.hpp +++ b/src/hotspot/cpu/x86/vmStructs_x86.hpp @@ -46,7 +46,7 @@ #define VM_LONG_CONSTANTS_CPU(declare_constant, declare_preprocessor_constant) -#define DECLARE_LONG_CPU_FEATURE_CONSTANT(id, name) GENERATE_VM_LONG_CONSTANT_ENTRY(VM_Version::CPU_##id) +#define DECLARE_LONG_CPU_FEATURE_CONSTANT(id, name, bit) GENERATE_VM_LONG_CONSTANT_ENTRY(VM_Version::CPU_##id) #define VM_LONG_CPU_FEATURE_CONSTANTS CPU_FEATURE_FLAGS(DECLARE_LONG_CPU_FEATURE_CONSTANT) #endif // CPU_X86_VMSTRUCTS_X86_HPP diff --git a/src/hotspot/cpu/x86/vm_version_x86.cpp b/src/hotspot/cpu/x86/vm_version_x86.cpp index 7f5dd408fa7..ca307fdefac 100644 --- a/src/hotspot/cpu/x86/vm_version_x86.cpp +++ b/src/hotspot/cpu/x86/vm_version_x86.cpp @@ -144,7 +144,7 @@ int VM_Version::_stepping; bool VM_Version::_has_intel_jcc_erratum; VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, }; -#define DECLARE_CPU_FEATURE_NAME(id, name) XSTR(name), +#define DECLARE_CPU_FEATURE_NAME(id, name, bit) name, const char* VM_Version::_features_names[] = { CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_NAME)}; #undef DECLARE_CPU_FEATURE_NAME diff --git a/src/hotspot/cpu/x86/vm_version_x86.hpp b/src/hotspot/cpu/x86/vm_version_x86.hpp index 82ab8a11325..f351ae46d8e 100644 --- a/src/hotspot/cpu/x86/vm_version_x86.hpp +++ b/src/hotspot/cpu/x86/vm_version_x86.hpp @@ -40,101 +40,104 @@ class VM_Feature_Flag { public: enum Feature_Flag { #define CPU_FEATURE_FLAGS(decl) \ - decl(CX8, cx8 ) /* next bits are from cpuid 1 (EDX) */ \ - decl(CMOV, cmov ) \ - decl(FXSR, fxsr ) \ - decl(HT, ht ) \ - \ - decl(MMX, mmx ) \ - decl(3DNOW_PREFETCH, 3dnowpref ) /* Processor supports 3dnow prefetch and prefetchw instructions */ \ - /* may not necessarily support other 3dnow instructions */ \ - decl(SSE, sse ) \ - decl(SSE2, sse2 ) \ - \ - decl(SSE3, sse3 ) /* SSE3 comes from cpuid 1 (ECX) */ \ - decl(SSSE3, ssse3 ) \ - decl(SSE4A, sse4a ) \ - decl(SSE4_1, sse4.1 ) \ - \ - decl(SSE4_2, sse4.2 ) \ - decl(POPCNT, popcnt ) \ - decl(LZCNT, lzcnt ) \ - decl(TSC, tsc ) \ - \ - decl(TSCINV_BIT, tscinvbit ) \ - decl(TSCINV, tscinv ) \ - decl(AVX, avx ) \ - decl(AVX2, avx2 ) \ - \ - decl(AES, aes ) \ - decl(ERMS, erms ) /* enhanced 'rep movsb/stosb' instructions */ \ - decl(CLMUL, clmul ) /* carryless multiply for CRC */ \ - decl(BMI1, bmi1 ) \ - \ - decl(BMI2, bmi2 ) \ - decl(RTM, rtm ) /* Restricted Transactional Memory instructions */ \ - decl(ADX, adx ) \ - decl(AVX512F, avx512f ) /* AVX 512bit foundation instructions */ \ - \ - decl(AVX512DQ, avx512dq ) \ - decl(AVX512PF, avx512pf ) \ - decl(AVX512ER, avx512er ) \ - decl(AVX512CD, avx512cd ) \ - \ - decl(AVX512BW, avx512bw ) /* Byte and word vector instructions */ \ - decl(AVX512VL, avx512vl ) /* EVEX instructions with smaller vector length */ \ - decl(SHA, sha ) /* SHA instructions */ \ - decl(FMA, fma ) /* FMA instructions */ \ - \ - decl(VZEROUPPER, vzeroupper ) /* Vzeroupper instruction */ \ - decl(AVX512_VPOPCNTDQ, avx512_vpopcntdq ) /* Vector popcount */ \ - decl(AVX512_VPCLMULQDQ, avx512_vpclmulqdq) /* Vector carryless multiplication */ \ - decl(AVX512_VAES, avx512_vaes ) /* Vector AES instruction */ \ - \ - decl(AVX512_VNNI, avx512_vnni ) /* Vector Neural Network Instructions */ \ - decl(FLUSH, clflush ) /* flush instruction */ \ - decl(FLUSHOPT, clflushopt ) /* flusopth instruction */ \ - decl(CLWB, clwb ) /* clwb instruction */ \ - \ - decl(AVX512_VBMI2, avx512_vbmi2 ) /* VBMI2 shift left double instructions */ \ - decl(AVX512_VBMI, avx512_vbmi ) /* Vector BMI instructions */ \ - decl(HV, hv ) /* Hypervisor instructions */ \ - decl(SERIALIZE, serialize ) /* CPU SERIALIZE */ \ - decl(RDTSCP, rdtscp ) /* RDTSCP instruction */ \ - decl(RDPID, rdpid ) /* RDPID instruction */ \ - decl(FSRM, fsrm ) /* Fast Short REP MOV */ \ - decl(GFNI, gfni ) /* Vector GFNI instructions */ \ - decl(AVX512_BITALG, avx512_bitalg ) /* Vector sub-word popcount and bit gather instructions */\ - decl(F16C, f16c ) /* Half-precision and single precision FP conversion instructions*/ \ - decl(PKU, pku ) /* Protection keys for user-mode pages */ \ - decl(OSPKE, ospke ) /* OS enables protection keys */ \ - decl(CET_IBT, cet_ibt ) /* Control Flow Enforcement - Indirect Branch Tracking */ \ - decl(CET_SS, cet_ss ) /* Control Flow Enforcement - Shadow Stack */ \ - decl(AVX512_IFMA, avx512_ifma ) /* Integer Vector FMA instructions*/ \ - decl(AVX_IFMA, avx_ifma ) /* 256-bit VEX-coded variant of AVX512-IFMA*/ \ - decl(APX_F, apx_f ) /* Intel Advanced Performance Extensions*/ \ - decl(SHA512, sha512 ) /* SHA512 instructions*/ \ - decl(AVX512_FP16, avx512_fp16 ) /* AVX512 FP16 ISA support*/ \ - decl(AVX10_1, avx10_1 ) /* AVX10 512 bit vector ISA Version 1 support*/ \ - decl(AVX10_2, avx10_2 ) /* AVX10 512 bit vector ISA Version 2 support*/ \ - decl(HYBRID, hybrid ) /* Hybrid architecture */ \ - decl(FMA4, fma4 ) \ - decl(MOVBE, movbe ) \ - decl(OSXSAVE, osxsave ) \ - decl(IBT, ibt ) \ - decl(SHSTK, shstk ) /* Also known as cet_ss */ \ - decl(XSAVE, xsave ) \ - decl(CMPXCHG16, cmpxchg16 ) /* Also known in cpuinfo as cx16 and in glibc as cmpxchg16b */ \ - decl(LAHFSAHF, lahfsahf ) /* Also known in cpuinfo as lahf_lm and in glibc as lahf64_sahf64 */ \ - decl(HTT, htt ) /* hotspot calls it 'ht' but that is affected by threads_per_core() */ \ - decl(XSAVEC, xsavec ) \ - decl(AVX_Fast_Unaligned_Load, avx_fast_unaligned_load) \ + decl(CX8, "cx8", 0) /* next bits are from cpuid 1 (EDX) */ \ + decl(CMOV, "cmov", 1) \ + decl(FXSR, "fxsr", 2) \ + decl(HT, "ht", 3) \ + \ + decl(MMX, "mmx", 4) \ + decl(3DNOW_PREFETCH, "3dnowpref", 5) /* Processor supports 3dnow prefetch and prefetchw instructions */ \ + /* may not necessarily support other 3dnow instructions */ \ + decl(SSE, "sse", 6) \ + decl(SSE2, "sse2", 7) \ + \ + decl(SSE3, "sse3", 8 ) /* SSE3 comes from cpuid 1 (ECX) */ \ + decl(SSSE3, "ssse3", 9 ) \ + decl(SSE4A, "sse4a", 10) \ + decl(SSE4_1, "sse4.1", 11) \ + \ + decl(SSE4_2, "sse4.2", 12) \ + decl(POPCNT, "popcnt", 13) \ + decl(LZCNT, "lzcnt", 14) \ + decl(TSC, "tsc", 15) \ + \ + decl(TSCINV_BIT, "tscinvbit", 16) \ + decl(TSCINV, "tscinv", 17) \ + decl(AVX, "avx", 18) \ + decl(AVX2, "avx2", 19) \ + \ + decl(AES, "aes", 20) \ + decl(ERMS, "erms", 21) /* enhanced 'rep movsb/stosb' instructions */ \ + decl(CLMUL, "clmul", 22) /* carryless multiply for CRC */ \ + decl(BMI1, "bmi1", 23) \ + \ + decl(BMI2, "bmi2", 24) \ + decl(RTM, "rtm", 25) /* Restricted Transactional Memory instructions */ \ + decl(ADX, "adx", 26) \ + decl(AVX512F, "avx512f", 27) /* AVX 512bit foundation instructions */ \ + \ + decl(AVX512DQ, "avx512dq", 28) \ + decl(AVX512PF, "avx512pf", 29) \ + decl(AVX512ER, "avx512er", 30) \ + decl(AVX512CD, "avx512cd", 31) \ + \ + decl(AVX512BW, "avx512bw", 32) /* Byte and word vector instructions */ \ + decl(AVX512VL, "avx512vl", 33) /* EVEX instructions with smaller vector length */ \ + decl(SHA, "sha", 34) /* SHA instructions */ \ + decl(FMA, "fma", 35) /* FMA instructions */ \ + \ + decl(VZEROUPPER, "vzeroupper", 36) /* Vzeroupper instruction */ \ + decl(AVX512_VPOPCNTDQ, "avx512_vpopcntdq", 37) /* Vector popcount */ \ + decl(AVX512_VPCLMULQDQ, "avx512_vpclmulqdq", 38) /* Vector carryless multiplication */ \ + decl(AVX512_VAES, "avx512_vaes", 39) /* Vector AES instruction */ \ + \ + decl(AVX512_VNNI, "avx512_vnni", 40) /* Vector Neural Network Instructions */ \ + decl(FLUSH, "clflush", 41) /* flush instruction */ \ + decl(FLUSHOPT, "clflushopt", 42) /* flusopth instruction */ \ + decl(CLWB, "clwb", 43) /* clwb instruction */ \ + \ + decl(AVX512_VBMI2, "avx512_vbmi2", 44) /* VBMI2 shift left double instructions */ \ + decl(AVX512_VBMI, "avx512_vbmi", 45) /* Vector BMI instructions */ \ + decl(HV, "hv", 46) /* Hypervisor instructions */ \ + decl(SERIALIZE, "serialize", 47) /* CPU SERIALIZE */ \ + decl(RDTSCP, "rdtscp", 48) /* RDTSCP instruction */ \ + decl(RDPID, "rdpid", 49) /* RDPID instruction */ \ + decl(FSRM, "fsrm", 50) /* Fast Short REP MOV */ \ + decl(GFNI, "gfni", 51) /* Vector GFNI instructions */ \ + decl(AVX512_BITALG, "avx512_bitalg", 52) /* Vector sub-word popcount and bit gather instructions */\ + decl(F16C, "f16c", 53) /* Half-precision and single precision FP conversion instructions*/ \ + decl(PKU, "pku", 54) /* Protection keys for user-mode pages */ \ + decl(OSPKE, "ospke", 55) /* OS enables protection keys */ \ + decl(CET_IBT, "cet_ibt", 56) /* Control Flow Enforcement - Indirect Branch Tracking */ \ + decl(CET_SS, "cet_ss", 57) /* Control Flow Enforcement - Shadow Stack */ \ + decl(AVX512_IFMA, "avx512_ifma", 58) /* Integer Vector FMA instructions*/ \ + decl(AVX_IFMA, "avx_ifma", 59) /* 256-bit VEX-coded variant of AVX512-IFMA*/ \ + decl(APX_F, "apx_f", 60) /* Intel Advanced Performance Extensions*/ \ + decl(SHA512, "sha512", 61) /* SHA512 instructions*/ \ + decl(AVX512_FP16, "avx512_fp16", 62) /* AVX512 FP16 ISA support*/ \ + decl(AVX10_1, "avx10_1", 63) /* AVX10 512 bit vector ISA Version 1 support*/ \ + decl(AVX10_2, "avx10_2", 64) /* AVX10 512 bit vector ISA Version 2 support*/ \ + decl(HYBRID, "hybrid", 65) /* Hybrid architecture */ \ + /* These features are added for CRaC for GLIBC_TUNABLES=glibc.cpu.hwcaps . */ \ + decl(FMA4, "fma4", 117) \ + decl(MOVBE, "movbe", 118) \ + decl(OSXSAVE, "osxsave", 119) \ + decl(IBT, "ibt", 120) \ + decl(SHSTK, "shstk", 121) /* Also known as cet_ss */ \ + decl(XSAVE, "xsave", 122) \ + decl(CMPXCHG16, "cmpxchg16", 123) /* Also known in cpuinfo as cx16 and in glibc as cmpxchg16b */ \ + decl(LAHFSAHF, "lahfsahf", 124) /* Also known in cpuinfo as lahf_lm and in glibc as lahf64_sahf64 */ \ + decl(HTT, "htt", 125) /* hotspot calls it 'ht' but that is affected by threads_per_core() */ \ + decl(XSAVEC, "xsavec", 126) \ + decl(AVX_Fast_Unaligned_Load, "avx_fast_unaligned_load", 127) \ /**/ -#define DECLARE_CPU_FEATURE_FLAG(id, name) CPU_##id, +#define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (bit), CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG) #undef DECLARE_CPU_FEATURE_FLAG - MAX_CPU_FEATURES + MAX_CPU_FEATURES, + // Define a window of unused features so that adding new CPU_* upstream does not shift the GLIBC features. + FIRST_GLIBC_FEATURE = CPU_FMA4 }; }; diff --git a/src/hotspot/share/jvmci/vmStructs_jvmci.cpp b/src/hotspot/share/jvmci/vmStructs_jvmci.cpp index 4a1ddf13d60..1fdf98588fd 100644 --- a/src/hotspot/share/jvmci/vmStructs_jvmci.cpp +++ b/src/hotspot/share/jvmci/vmStructs_jvmci.cpp @@ -1017,7 +1017,7 @@ static_field(VM_Version, _rop_protection, bool) \ volatile_nonstatic_field(JavaFrameAnchor, _last_Java_fp, intptr_t*) -#define DECLARE_INT_CPU_FEATURE_CONSTANT(id, name) GENERATE_VM_INT_CONSTANT_ENTRY(VM_Version::CPU_##id) +#define DECLARE_INT_CPU_FEATURE_CONSTANT(id, name, bit) GENERATE_VM_INT_CONSTANT_ENTRY(VM_Version::CPU_##id) #define VM_INT_CPU_FEATURE_CONSTANTS CPU_FEATURE_FLAGS(DECLARE_INT_CPU_FEATURE_CONSTANT) #endif @@ -1037,7 +1037,7 @@ declare_constant(frame::interpreter_frame_sender_sp_offset) \ declare_constant(frame::interpreter_frame_last_sp_offset) -#define DECLARE_LONG_CPU_FEATURE_CONSTANT(id, name) GENERATE_VM_LONG_CONSTANT_ENTRY(VM_Version::CPU_##id) +#define DECLARE_LONG_CPU_FEATURE_CONSTANT(id, name, bit) GENERATE_VM_LONG_CONSTANT_ENTRY(VM_Version::CPU_##id) #define VM_LONG_CPU_FEATURE_CONSTANTS \ CPU_FEATURE_FLAGS(DECLARE_LONG_CPU_FEATURE_CONSTANT) diff --git a/src/hotspot/share/runtime/abstract_vm_version.inline.hpp b/src/hotspot/share/runtime/abstract_vm_version.inline.hpp index 64aac28a7cd..a8e8c216232 100644 --- a/src/hotspot/share/runtime/abstract_vm_version.inline.hpp +++ b/src/hotspot/share/runtime/abstract_vm_version.inline.hpp @@ -254,6 +254,14 @@ bool VM_Version::glibc_not_using() { VM_Features all_features; all_features.set_all_features(); + if (FIRST_GLIBC_FEATURE != MAX_CPU_FEATURES) { + assert(handled.supports_feature(FIRST_GLIBC_FEATURE), "FIRST_GLIBC_FEATURE not handled"); + VM_Feature_Flag::Feature_Flag last_cpu = static_cast(static_cast(FIRST_GLIBC_FEATURE) - 1); + while (!handled.supports_feature(last_cpu)) { + all_features.clear_feature(last_cpu); + last_cpu = static_cast(static_cast(last_cpu) - 1); + } + } if (handled != all_features) { stringStream ss; ss.print_raw("internal error: Unsupported disabling of some CPU_* "); diff --git a/test/jdk/jdk/crac/CPUFeatures/CPUFeaturesAWS.sh b/test/jdk/jdk/crac/CPUFeatures/CPUFeaturesAWS.sh index 224f066b318..88175098400 100755 --- a/test/jdk/jdk/crac/CPUFeatures/CPUFeaturesAWS.sh +++ b/test/jdk/jdk/crac/CPUFeatures/CPUFeaturesAWS.sh @@ -246,6 +246,7 @@ checkpoint_restore_one() { kind=$kind_checkpoint setup snapshot="$(runssh "./CPUFeaturesAWS.sh internal_checkpoint $enginecmdline $checkpoint_args" 2>&1|tee /proc/self/fd/2)" + local r="$engine" if [ "$expectrc" = -1 ] && echo "$snapshot"|grep "$expect_error";then r="$r-PASS" else @@ -255,7 +256,6 @@ checkpoint_restore_one() { runssh "rm -rf cr;ssh -o 'UserKnownHostsFile /dev/null' -o 'StrictHostKeyChecking no' -i key $(ipaddr $kind_checkpoint) tar cf - cr|tar xf -" fi restore="$(runssh "./CPUFeaturesAWS.sh internal_restore $enginecmdline $restore_args" 2>&1|tee /proc/self/fd/2)" - local r="$engine" if echo "$restore"|grep -w RC=$expectrc && echo "$restore"|grep "$expect_error";then r="$r-PASS" else @@ -290,7 +290,7 @@ if echo "$arch"|grep -q ', x86-64, ';then # Test 2 issues: # 1: ZULU-84672: CPUFeatures: Intel/AMD image portability problem; non-contained intersection; a!=(a&b)!=b # 2: IgnoreCPUFeatures is not inherited from snapshot to restore. -checkpoint_restore "$LINENO" t3a.micro t3.micro "1:Restore failed due to incompatible or missing CPU features, try using -XX:CPUFeatures=0x21461805ddfbf7,0xfcc on checkpoint." \ +checkpoint_restore "$LINENO" t3a.micro t3.micro "1:Restore failed due to incompatible or missing CPU features, try using -XX:CPUFeatures=0x21461805ddfbf7,0xfcc0000000000000 on checkpoint." \ "-XX:+UnlockExperimentalVMOptions -XX:+IgnoreCPUFeatures" "" # Test IgnoreCPUFeatures - in this case it only works by luck. @@ -303,13 +303,13 @@ checkpoint_restore "$LINENO" t3a.micro t3.micro "1:VM option .*CPUFeatures.* is # Test printing during snapshot: "CPU features are being kept intact as requested by -XX:CPUFeatures=ignore" checkpoint_restore "$LINENO" t3a.micro t3.micro "" "-XX:CPUFeatures=ignore" "-XX:+UnlockExperimentalVMOptions -XX:+IgnoreCPUFeatures" -checkpoint_restore "$LINENO" t3a.micro t3.micro "" "-XX:CPUFeatures=0x21461805ddfbf7,0xfcc" -checkpoint_restore "$LINENO" t3.micro t3a.micro "" "-XX:CPUFeatures=0x21461805ddfbf7,0xfcc" +checkpoint_restore "$LINENO" t3a.micro t3.micro "" "-XX:CPUFeatures=0x21461805ddfbf7,0xfcc0000000000000" +checkpoint_restore "$LINENO" t3.micro t3a.micro "" "-XX:CPUFeatures=0x21461805ddfbf7,0xfcc0000000000000" checkpoint_restore "$LINENO" m1.small t3.micro # criu FAIL: JDK-8373027: [CRaC] [CRIU] x86: FPU xsave area present, but host cpu doesn't support it -checkpoint_restore "$LINENO" t3.micro m1.small "" "-XX:CPUFeatures=0x142000070bbd7,0x380" "" +checkpoint_restore "$LINENO" t3.micro m1.small "" "-XX:CPUFeatures=0x142000070bbd7,0x3800000000000000" "" checkpoint_restore "$LINENO" t3.micro t3.micro "" "-XX:CPUFeatures=native" "" @@ -320,7 +320,7 @@ checkpoint_restore "$LINENO" t3.micro t3.micro "" "-XX:CPUFeatures=generic" "" # Currently the most modern x86_64 CPU in AWS. # criu FAIL: ZULU-84505: [CRaC] [CRIU] Fix a failure for checkpoint on AWS m8i-flex.large -checkpoint_restore "$LINENO" m8i-flex.large m1.small "" "-XX:CPUFeatures=0x142000070bbd7,0x380" "" +checkpoint_restore "$LINENO" m8i-flex.large m1.small "" "-XX:CPUFeatures=0x142000070bbd7,0x3800000000000000" "" # 8374491: CPUFeatures: check performance regression of AVX_Fast_Unaligned_Load lastline="$LINENO" @@ -342,14 +342,14 @@ elif echo "$arch"|grep -q ', ARM aarch64, ';then checkpoint_restore "$LINENO" a1.medium a1.medium checkpoint_restore "$LINENO" t4g.micro t4g.micro checkpoint_restore "$LINENO" a1.medium t4g.micro -checkpoint_restore "$LINENO" t4g.micro a1.medium "1:Restore failed due to incompatible or missing CPU features, try using -XX:CPUFeatures=0x4000ff on checkpoint." -checkpoint_restore "$LINENO" t4g.micro a1.medium "-1:LSE (0x100) cannot be disabled via -XX:CPUFeatures on aarch64." "-XX:CPUFeatures=0x4000ff" "" +checkpoint_restore "$LINENO" t4g.micro a1.medium "1:Restore failed due to incompatible or missing CPU features, try using -XX:CPUFeatures=0x80000000000000ff on checkpoint." +checkpoint_restore "$LINENO" t4g.micro a1.medium "-1:LSE (0x100) cannot be disabled via -XX:CPUFeatures on aarch64." "-XX:CPUFeatures=0x80000000000000ff" "" -checkpoint_restore "$LINENO" c7g.medium c7g.medium -checkpoint_restore "$LINENO" c8g.medium c8g.medium +# JDK-8385359: checkpoint_restore "$LINENO" c7g.medium c7g.medium +# JDK-8385359: checkpoint_restore "$LINENO" c8g.medium c8g.medium # JDK-8385359: checkpoint_restore "$LINENO" c7g.medium c8g.medium checkpoint_restore "$LINENO" c8g.medium c7g.medium "1:Restore failed due to incompatible or missing CPU features, try using -XX:CPUFeatures=0x17fff on checkpoint." -checkpoint_restore "$LINENO" c8g.medium c7g.medium "" "-XX:CPUFeatures=0x17fff" "" +# JDK-8385359: checkpoint_restore "$LINENO" c8g.medium c7g.medium "" "-XX:CPUFeatures=0x17fff" "" checkpoint_restore "$LINENO" t4g.micro c8g.medium "1:Restore failed due to incompatible aarch64 CPU feature PACA (0x10000); these CPUs each require a separate image." checkpoint_restore "$LINENO" c8g.medium t4g.micro "1:Restore failed due to incompatible aarch64 CPU feature PACA (0x10000); these CPUs each require a separate image." diff --git a/test/jdk/jdk/crac/CPUFeatures/SimpleCPUFeaturesTest.java b/test/jdk/jdk/crac/CPUFeatures/SimpleCPUFeaturesTest.java index b75985aea1b..70e9c8d243e 100644 --- a/test/jdk/jdk/crac/CPUFeatures/SimpleCPUFeaturesTest.java +++ b/test/jdk/jdk/crac/CPUFeatures/SimpleCPUFeaturesTest.java @@ -72,7 +72,7 @@ * @requires os.arch=="aarch64" * @library /test/lib * @build SimpleCPUFeaturesTest - * @run driver jdk.test.lib.crac.CracTest 0x0 + * @run driver jdk.test.lib.crac.CracTest 0x0 -- INVALID_PACA * @run driver jdk.test.lib.crac.CracTest 0x0,0x0 -- INVALID_FORMAT1 * @run driver jdk.test.lib.crac.CracTest foobar -- INVALID_FORMAT1 */ @@ -92,6 +92,7 @@ public class SimpleCPUFeaturesTest implements CracTest { private enum ErrorMsg { INVALID_FORMAT1("must be of the form: 0xNUM"), INVALID_FORMAT2("must be of the form: 0xNUM,0xNUM"), + INVALID_PACA("For -XX:CPUFeatures, exactly one of the bits PACA (0x10000) and NOTPACA (0x100000) must be set."), MISSING_FEATURES("missing features of this CPU are"), ARCH_DOES_NOT_SUPPORT("This architecture does not support any arch-specific"), OS_DOES_NOT_SUPPORT("This OS does not support"), diff --git a/test/jdk/jdk/crac/engine/CheckCPUFeaturesTest.java b/test/jdk/jdk/crac/engine/CheckCPUFeaturesTest.java index 5b68e47fd0e..df0288c7cca 100644 --- a/test/jdk/jdk/crac/engine/CheckCPUFeaturesTest.java +++ b/test/jdk/jdk/crac/engine/CheckCPUFeaturesTest.java @@ -42,11 +42,11 @@ * @run driver jdk.test.lib.crac.CracTest native skip fail * @run driver jdk.test.lib.crac.CracTest native skip-experimental pass * @run driver jdk.test.lib.crac.CracTest generic compatible pass - * @run driver jdk.test.lib.crac.CracTest generic exact fail-x86 + * @run driver jdk.test.lib.crac.CracTest generic exact fail-x86aarch64 * @run driver jdk.test.lib.crac.CracTest generic skip fail * @run driver jdk.test.lib.crac.CracTest generic skip-experimental pass - * @run driver jdk.test.lib.crac.CracTest ignore compatible fail-x86 - * @run driver jdk.test.lib.crac.CracTest ignore exact fail-x86 + * @run driver jdk.test.lib.crac.CracTest ignore compatible fail-x86aarch64 + * @run driver jdk.test.lib.crac.CracTest ignore exact fail-x86aarch64 * @run driver jdk.test.lib.crac.CracTest ignore skip fail * @run driver jdk.test.lib.crac.CracTest ignore skip-experimental pass */ @@ -63,8 +63,8 @@ public class CheckCPUFeaturesTest implements CracTest { @Override public void test() throws Exception { boolean success = "pass".equals(result); - if (!Platform.isX86() && !Platform.isX64()) { - success = success || "fail-x86".equals(result); + if (!Platform.isX86() && !Platform.isX64() && !Platform.isAArch64()) { + success = success || "fail-x86aarch64".equals(result); } CracBuilder builder = new CracBuilder().engine(CracEngine.PAUSE);