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luciechoiluciechoi
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Merge branch 'main' into texture2dms
2 parents 2dca0c2 + e68408d commit 487f304

11 files changed

Lines changed: 1202 additions & 195 deletions

‎lib/API/MTL/MTLDevice.cpp‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,7 @@
1212
#include "API/Device.h"
1313
#include "Support/Pipeline.h"
1414

15+
#include "llvm/ADT/ScopeExit.h"
1516
#include "llvm/ADT/SmallString.h"
1617
#include "llvm/Support/Error.h"
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#include "llvm/Support/JSON.h"
@@ -405,6 +406,9 @@ class MTLDevice : public offloadtest::Device {
405406
MTL::ComputeCommandEncoder *CmdEncoder =
406407
IS.CmdBuffer->computeCommandEncoder();
407408

409+
auto CloseCommandEncoder =
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llvm::scope_exit([&]() { CmdEncoder->endEncoding(); });
411+
408412
CmdEncoder->setComputePipelineState(IS.ComputePipeline);
409413
CmdEncoder->setBuffer(IS.ArgBuffer, 0, 2);
410414
for (uint64_t I = 0; I < IS.Textures.size(); ++I)
@@ -463,7 +467,6 @@ class MTLDevice : public offloadtest::Device {
463467
CmdEncoder->dispatchThreads(GridSize, GroupSize);
464468
CmdEncoder->memoryBarrier(MTL::BarrierScopeBuffers);
465469

466-
CmdEncoder->endEncoding();
467470
return llvm::Error::success();
468471
}
469472

‎test/Basic/Matrix/matrix_groupthread_swizzle_one_based.test‎

Lines changed: 122 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,122 @@
1+
#--- source.hlsl
2+
3+
RWBuffer<int> In : register(u0);
4+
RWBuffer<int> RowOut : register(u1);
5+
RWBuffer<int> ColOut : register(u2);
6+
7+
[numthreads(4,1,1)]
8+
void main(uint GI : SV_GroupIndex) {
9+
int4x4 A;
10+
int4x4 B;
11+
switch(GI) {
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case 0:
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A._11_12_13_14 = In[GI].xxxx;
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B._11_21_31_41 = In[GI].xxxx;
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break;
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case 1:
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A._21_22_23_24 = In[GI].xxxx;
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B._12_22_32_42 = In[GI].xxxx;
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break;
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case 2:
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A._31_32_33_34 = In[GI].xxxx;
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B._13_23_33_43 = In[GI].xxxx;
23+
break;
24+
case 3:
25+
A._41_42_43_44 = In[GI].xxxx;
26+
B._14_24_34_44 = In[GI].xxxx;
27+
break;
28+
29+
}
30+
int4 vec1;
31+
int4 vec2;
32+
switch(GI) {
33+
case 0:
34+
vec1 = A._11_12_13_14;
35+
vec2 = B._11_21_31_41;
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break;
37+
case 1:
38+
vec1 = A._21_22_23_24;
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vec2 = B._12_22_32_42;
40+
break;
41+
case 2:
42+
vec1 = A._31_32_33_34;
43+
vec2 = B._13_23_33_43;
44+
break;
45+
case 3:
46+
vec1 = A._41_42_43_44;
47+
vec2 = B._14_24_34_44;
48+
break;
49+
}
50+
for(int i = 0; i < 4; i++) {
51+
RowOut[GI*4+i] = vec1[i];
52+
ColOut[i*4+GI] = vec2[i];
53+
}
54+
}
55+
56+
//--- pipeline.yaml
57+
58+
---
59+
Shaders:
60+
- Stage: Compute
61+
Entry: main
62+
DispatchSize: [1, 1, 1]
63+
Buffers:
64+
- Name: In
65+
Format: Int32
66+
Data: [ 1, 2, 3, 4]
67+
- Name: RowOut
68+
Format: Int32
69+
FillSize: 64
70+
- Name: ColOut
71+
Format: Int32
72+
FillSize: 64
73+
- Name: ExpectedRowOut
74+
Format: Int32
75+
Data: [ 1,1,1,1, 2,2,2,2, 3,3,3,3, 4,4,4,4 ]
76+
- Name: ExpectedColOut
77+
Format: Int32
78+
Data: [ 1,2,3,4, 1,2,3,4, 1,2,3,4, 1,2,3,4 ]
79+
Results:
80+
- Result: RowOut
81+
Rule: BufferExact
82+
Actual: RowOut
83+
Expected: ExpectedRowOut
84+
- Result: ColOut
85+
Rule: BufferExact
86+
Actual: ColOut
87+
Expected: ExpectedColOut
88+
DescriptorSets:
89+
- Resources:
90+
- Name: In
91+
Kind: RWBuffer
92+
DirectXBinding:
93+
Register: 0
94+
Space: 0
95+
VulkanBinding:
96+
Binding: 0
97+
- Name: RowOut
98+
Kind: RWBuffer
99+
DirectXBinding:
100+
Register: 1
101+
Space: 0
102+
VulkanBinding:
103+
Binding: 1
104+
- Name: ColOut
105+
Kind: RWBuffer
106+
DirectXBinding:
107+
Register: 2
108+
Space: 0
109+
VulkanBinding:
110+
Binding: 2
111+
...
112+
#--- end
113+
114+
# BUG https://github.com/llvm/llvm-project/issues/180258
115+
# XFAIL: Vulkan && Clang
116+
117+
# BUG https://github.com/llvm/llvm-project/issues/191511
118+
# XFAIL: (Metal || DirectX) && Clang
119+
120+
# RUN: split-file %s %t
121+
# RUN: %dxc_target -T cs_6_0 -Fo %t.o %t/source.hlsl
122+
# RUN: %offloader %t/pipeline.yaml %t.o

‎test/Basic/Matrix/matrix_groupthread_swizzle_zero_based.test‎

Lines changed: 122 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,122 @@
1+
#--- source.hlsl
2+
3+
RWBuffer<int> In : register(u0);
4+
RWBuffer<int> RowOut : register(u1);
5+
RWBuffer<int> ColOut : register(u2);
6+
7+
[numthreads(4,1,1)]
8+
void main(uint GI : SV_GroupIndex) {
9+
int4x4 A;
10+
int4x4 B;
11+
switch(GI) {
12+
case 0:
13+
A._m00_m01_m02_m03 = In[GI].xxxx;
14+
B._m00_m10_m20_m30 = In[GI].xxxx;
15+
break;
16+
case 1:
17+
A._m10_m11_m12_m13 = In[GI].xxxx;
18+
B._m01_m11_m21_m31 = In[GI].xxxx;
19+
break;
20+
case 2:
21+
A._m20_m21_m22_m23 = In[GI].xxxx;
22+
B._m02_m12_m22_m32 = In[GI].xxxx;
23+
break;
24+
case 3:
25+
A._m30_m31_m32_m33 = In[GI].xxxx;
26+
B._m03_m13_m23_m33 = In[GI].xxxx;
27+
break;
28+
29+
}
30+
int4 vec1;
31+
int4 vec2;
32+
switch(GI) {
33+
case 0:
34+
vec1 = A._m00_m01_m02_m03;
35+
vec2 = B._m00_m10_m20_m30;
36+
break;
37+
case 1:
38+
vec1 = A._m10_m11_m12_m13;
39+
vec2 = B._m01_m11_m21_m31;
40+
break;
41+
case 2:
42+
vec1 = A._m20_m21_m22_m23;
43+
vec2 = B._m02_m12_m22_m32;
44+
break;
45+
case 3:
46+
vec1 = A._m30_m31_m32_m33;
47+
vec2 = B._m03_m13_m23_m33;
48+
break;
49+
}
50+
for(int i = 0; i < 4; i++) {
51+
RowOut[GI*4+i] = vec1[i];
52+
ColOut[i*4+GI] = vec2[i];
53+
}
54+
}
55+
56+
//--- pipeline.yaml
57+
58+
---
59+
Shaders:
60+
- Stage: Compute
61+
Entry: main
62+
DispatchSize: [1, 1, 1]
63+
Buffers:
64+
- Name: In
65+
Format: Int32
66+
Data: [ 1, 2, 3, 4]
67+
- Name: RowOut
68+
Format: Int32
69+
FillSize: 64
70+
- Name: ColOut
71+
Format: Int32
72+
FillSize: 64
73+
- Name: ExpectedRowOut
74+
Format: Int32
75+
Data: [ 1,1,1,1, 2,2,2,2, 3,3,3,3, 4,4,4,4 ]
76+
- Name: ExpectedColOut
77+
Format: Int32
78+
Data: [ 1,2,3,4, 1,2,3,4, 1,2,3,4, 1,2,3,4 ]
79+
Results:
80+
- Result: RowOut
81+
Rule: BufferExact
82+
Actual: RowOut
83+
Expected: ExpectedRowOut
84+
- Result: ColOut
85+
Rule: BufferExact
86+
Actual: ColOut
87+
Expected: ExpectedColOut
88+
DescriptorSets:
89+
- Resources:
90+
- Name: In
91+
Kind: RWBuffer
92+
DirectXBinding:
93+
Register: 0
94+
Space: 0
95+
VulkanBinding:
96+
Binding: 0
97+
- Name: RowOut
98+
Kind: RWBuffer
99+
DirectXBinding:
100+
Register: 1
101+
Space: 0
102+
VulkanBinding:
103+
Binding: 1
104+
- Name: ColOut
105+
Kind: RWBuffer
106+
DirectXBinding:
107+
Register: 2
108+
Space: 0
109+
VulkanBinding:
110+
Binding: 2
111+
...
112+
#--- end
113+
114+
# BUG Vulkan https://github.com/llvm/llvm-project/issues/180258
115+
# XFAIL: Vulkan && Clang
116+
117+
# BUG https://github.com/llvm/llvm-project/issues/191511
118+
# XFAIL: (Metal || DirectX) && Clang
119+
120+
# RUN: split-file %s %t
121+
# RUN: %dxc_target -T cs_6_0 -Fo %t.o %t/source.hlsl
122+
# RUN: %offloader %t/pipeline.yaml %t.o

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