diff --git a/components/university/university-flow-banner.tsx b/components/university/university-flow-banner.tsx index 153b70a..7a2ba91 100644 --- a/components/university/university-flow-banner.tsx +++ b/components/university/university-flow-banner.tsx @@ -162,7 +162,6 @@ export default function UniversityFlowBanner() { } jumpType={jumpGap === 0 ? "standing" : "running"} /> - {/* Premium Minimal Wind Waves */} {isJumping && ( @@ -270,7 +269,6 @@ export default function UniversityFlowBanner() { )} - {activeStep === steps.length - 1 && !isJumping && ( <> {/* Minimal Radial Burst */} diff --git a/content/rgpv/cse/semester-4/cs-403/pyqs.json b/content/rgpv/cse/semester-4/cs-403/pyqs.json index 5bfcc42..4624c3b 100644 --- a/content/rgpv/cse/semester-4/cs-403/pyqs.json +++ b/content/rgpv/cse/semester-4/cs-403/pyqs.json @@ -2,8 +2,984 @@ "subject": { "id": "cs-403", "code": "CS-403", - "name": "Software Engineering (SE)", - "title": "CS-403 - Software Engineering (SE)" + "name": "Software Engineering", + "title": "AL/CD/CS/CT/CO/SD-403 (GS) – Software Engineering", + "semester": "IV", + "gradingSystem": "Grading System (GS)", + "maxMarks": 70, + "time": "3 Hours", + "commonInstructions": [ + "Attempt any five questions.", + "All questions carry equal marks." + ] }, - "papers": [] + "papers": [ + { + "exam": "November 2022", + "year": 2022, + "month": "November", + "questions": [ + { + "id": "q1", + "questionNumber": "Q.1", + "subQuestions": [ + { + "id": "q1a", + "label": "a)", + "text": "With a neat diagram explain about the component assembly model and rational unified process.", + "unit": "Unit 1", + "type": "process-models" + }, + { + "id": "q1b", + "label": "b)", + "text": "Write about the characteristics of software engineering.", + "unit": "Unit 1", + "type": "software-characteristics" + } + ] + }, + { + "id": "q2", + "questionNumber": "Q.2", + "subQuestions": [ + { + "id": "q2a", + "label": "a)", + "text": "Explain about the CMM levels.", + "unit": "Unit 1", + "type": "cmm" + }, + { + "id": "q2b", + "label": "b)", + "text": "Draw a use case diagram for booking a ticket in a reservation system.", + "unit": "Unit 2", + "type": "use-case" + } + ] + }, + { + "id": "q3", + "questionNumber": "Q.3", + "subQuestions": [ + { + "id": "q3a", + "label": "a)", + "text": "What is meant by software requirement elicitation. How the requirements can be specified.", + "unit": "Unit 2", + "type": "elicitation" + }, + { + "id": "q3b", + "label": "b)", + "text": "What is a model? Why it is needed in the development of software.", + "unit": "Unit 3", + "type": "design-modeling" + } + ] + }, + { + "id": "q4", + "questionNumber": "Q.4", + "subQuestions": [ + { + "id": "q4a", + "label": "a)", + "text": "Explain in detail about the design concepts and principles.", + "unit": "Unit 3", + "type": "design-concepts" + }, + { + "id": "q4b", + "label": "b)", + "text": "How architecture is used in the development of software. What are the different styles used for it? Explain any two of them.", + "unit": "Unit 3", + "type": "architectural-styles" + } + ] + }, + { + "id": "q5", + "questionNumber": "Q.5", + "subQuestions": [ + { + "id": "q5a", + "label": "a)", + "text": "How do you describe the architecture of the software intensive system based on the use of multiple, concurrent views.", + "unit": "Unit 3", + "type": "architectural-views" + }, + { + "id": "q5b", + "label": "b)", + "text": "Explain different specialized testing techniques.", + "unit": "Unit 4", + "type": "testing" + } + ] + }, + { + "id": "q6", + "questionNumber": "Q.6", + "subQuestions": [ + { + "id": "q6a", + "label": "a)", + "text": "What is the need of integration testing? Explain it with a neat figure.", + "unit": "Unit 4", + "type": "integration-testing" + }, + { + "id": "q6b", + "label": "b)", + "text": "What is software testing? What are the levels present in it? How unit testing is used for software.", + "unit": "Unit 4", + "type": "testing" + } + ] + }, + { + "id": "q7", + "questionNumber": "Q.7", + "subQuestions": [ + { + "id": "q7a", + "label": "a)", + "text": "Explain software configuration management in detail.", + "unit": "Unit 5", + "type": "scm" + }, + { + "id": "q7b", + "label": "b)", + "text": "Write the difference between the re-engineering and reverse engineering with diagrams.", + "unit": "Unit 5", + "type": "maintenance" + } + ] + }, + { + "id": "q8", + "questionNumber": "Q.8", + "subQuestions": [ + { + "id": "q8", + "label": "", + "text": "Write short notes on: a) Traceability b) Static Analysis c) Risk management.", + "unit": "Unit 2/4/5", + "type": "mixed" + } + ] + } + ] + }, + { + "exam": "June 2023", + "year": 2023, + "month": "June", + "questions": [ + { + "id": "q1", + "questionNumber": "Q.1", + "subQuestions": [ + { + "id": "q1a", + "label": "a)", + "text": "Discuss in detail about Evolutionary process model in software Engineering.", + "unit": "Unit 1", + "type": "process-models" + }, + { + "id": "q1b", + "label": "b)", + "text": "What is RAD Model and why it is important. Give the applications of RAD model.", + "unit": "Unit 1", + "type": "rad" + } + ] + }, + { + "id": "q2", + "questionNumber": "Q.2", + "subQuestions": [ + { + "id": "q2a", + "label": "a)", + "text": "The functional requirements specification of a system should be both complete and consistent. Substantiate with examples.", + "unit": "Unit 2", + "type": "requirements" + }, + { + "id": "q2b", + "label": "b)", + "text": "What is the use-case model and how to make it? Discuss the four basic parts of a use-case model.", + "unit": "Unit 2", + "type": "use-case" + } + ] + }, + { + "id": "q3", + "questionNumber": "Q.3", + "subQuestions": [ + { + "id": "q3a", + "label": "a)", + "text": "Discuss about the basic principles of software design in software engineering.", + "unit": "Unit 3", + "type": "design-principles" + }, + { + "id": "q3b", + "label": "b)", + "text": "What are SA and SD? Discuss about component based design and what are its advantages.", + "unit": "Unit 3", + "type": "sa-sd" + } + ] + }, + { + "id": "q4", + "questionNumber": "Q.4", + "subQuestions": [ + { + "id": "q4a", + "label": "a)", + "text": "What are the strategic approaches to software testing? Explain in detail.", + "unit": "Unit 4", + "type": "testing" + }, + { + "id": "q4b", + "label": "b)", + "text": "What is unit testing in software Engineering? Explain with suitable example.", + "unit": "Unit 4", + "type": "unit-testing" + } + ] + }, + { + "id": "q5", + "questionNumber": "Q.5", + "subQuestions": [ + { + "id": "q5a", + "label": "a)", + "text": "What is meant by software quality? Explain the metrics for maintenance.", + "unit": "Unit 5", + "type": "sqa" + }, + { + "id": "q5b", + "label": "b)", + "text": "Discuss about SCM function in software engineering with suitable example.", + "unit": "Unit 5", + "type": "scm" + } + ] + }, + { + "id": "q6", + "questionNumber": "Q.6", + "subQuestions": [ + { + "id": "q6a", + "label": "a)", + "text": "What is system testing. Discuss about different types of system testing.", + "unit": "Unit 4", + "type": "system-testing" + }, + { + "id": "q6b", + "label": "b)", + "text": "What are test metrics and its types? What is the purpose of testing metrics? Explain.", + "unit": "Unit 4", + "type": "test-metrics" + } + ] + }, + { + "id": "q7", + "questionNumber": "Q.7", + "subQuestions": [ + { + "id": "q7a", + "label": "a)", + "text": "What is the difference between product and process metric?", + "unit": "Unit 1", + "type": "metrics" + }, + { + "id": "q7b", + "label": "b)", + "text": "What is component model in software engineering? Explain with neat diagram.", + "unit": "Unit 3", + "type": "component-model" + } + ] + }, + { + "id": "q8", + "questionNumber": "Q.8", + "subQuestions": [ + { + "id": "q8", + "label": "", + "text": "Write short notes on any two: a) Object Models b) Black-Box Testing c) Program Comprehension Techniques d) Testing Tools.", + "unit": "Unit 2/4/5", + "type": "mixed" + } + ] + } + ] + }, + { + "exam": "November 2023", + "year": 2023, + "month": "November", + "questions": [ + { + "id": "q1", + "questionNumber": "Q.1", + "subQuestions": [ + { + "id": "q1a", + "label": "a)", + "text": "What is spiral model? Explain with neat diagram.", + "unit": "Unit 1", + "type": "spiral" + }, + { + "id": "q1b", + "label": "b)", + "text": "What is SDLC? Illustrate the phases of SDLC in software engineering.", + "unit": "Unit 1", + "type": "sdlc" + } + ] + }, + { + "id": "q2", + "questionNumber": "Q.2", + "subQuestions": [ + { + "id": "q2a", + "label": "a)", + "text": "What is the difference between function oriented modeling and object oriented modeling?", + "unit": "Unit 2", + "type": "analysis-modeling" + }, + { + "id": "q2b", + "label": "b)", + "text": "Discuss about system and software requirement specifications.", + "unit": "Unit 2", + "type": "srs" + } + ] + }, + { + "id": "q3", + "questionNumber": "Q.3", + "subQuestions": [ + { + "id": "q3a", + "label": "a)", + "text": "What is a design metrics? Explain the importance of design metrics.", + "unit": "Unit 3", + "type": "design-metrics" + }, + { + "id": "q3b", + "label": "b)", + "text": "Discuss about the function oriented design strategies in detail.", + "unit": "Unit 3", + "type": "function-oriented" + } + ] + }, + { + "id": "q4", + "questionNumber": "Q.4", + "subQuestions": [ + { + "id": "q4a", + "label": "a)", + "text": "What is software testing and system testing? Explain in detail.", + "unit": "Unit 4", + "type": "testing" + }, + { + "id": "q4b", + "label": "b)", + "text": "Discuss about integration testing with suitable example.", + "unit": "Unit 4", + "type": "integration-testing" + } + ] + }, + { + "id": "q5", + "questionNumber": "Q.5", + "subQuestions": [ + { + "id": "q5a", + "label": "a)", + "text": "What is risk and how to identify the risk in software engineering? Explain.", + "unit": "Unit 5", + "type": "risk" + }, + { + "id": "q5b", + "label": "b)", + "text": "Write the difference between reverse engineering and re-engineering.", + "unit": "Unit 5", + "type": "maintenance" + } + ] + }, + { + "id": "q6", + "questionNumber": "Q.6", + "subQuestions": [ + { + "id": "q6a", + "label": "a)", + "text": "What are the steps of acceptance testing? Explain in detail.", + "unit": "Unit 4", + "type": "acceptance-testing" + }, + { + "id": "q6b", + "label": "b)", + "text": "Explain the principles of risk assessment and mitigation.", + "unit": "Unit 5", + "type": "risk" + } + ] + }, + { + "id": "q7", + "questionNumber": "Q.7", + "subQuestions": [ + { + "id": "q7a", + "label": "a)", + "text": "Write about project scheduling and tracking.", + "unit": "Unit 5", + "type": "project-management" + }, + { + "id": "q7b", + "label": "b)", + "text": "Describe RUP and agile processes in detail.", + "unit": "Unit 1", + "type": "rup-agile" + } + ] + }, + { + "id": "q8", + "questionNumber": "Q.8", + "subQuestions": [ + { + "id": "q8", + "label": "", + "text": "Write short notes on any two: a) Structured methods b) White-Box Testing c) Feasibility Analysis d) Test Case Design.", + "unit": "Unit 3/4/5", + "type": "mixed" + } + ] + } + ] + }, + { + "exam": "June 2024", + "year": 2024, + "month": "June", + "questions": [ + { + "id": "q1", + "questionNumber": "Q.1", + "subQuestions": [ + { + "id": "q1a", + "label": "a)", + "text": "Elucidate the key features of the software process models with suitable examples?", + "unit": "Unit 1", + "type": "process-models" + }, + { + "id": "q1b", + "label": "b)", + "text": "Write about CMM (Capability Maturity Model) and how it is used for Software Quality?", + "unit": "Unit 1", + "type": "cmm" + } + ] + }, + { + "id": "q2", + "questionNumber": "Q.2", + "subQuestions": [ + { + "id": "q2a", + "label": "a)", + "text": "Draw and explain the spiral model with its advantages and disadvantages?", + "unit": "Unit 1", + "type": "spiral" + }, + { + "id": "q2b", + "label": "b)", + "text": "Discuss the components of a software requirement specification document?", + "unit": "Unit 2", + "type": "srs" + } + ] + }, + { + "id": "q3", + "questionNumber": "Q.3", + "subQuestions": [ + { + "id": "q3a", + "label": "a)", + "text": "Differentiate between functional and Non Functional requirements with suitable examples?", + "unit": "Unit 2", + "type": "requirements" + }, + { + "id": "q3b", + "label": "b)", + "text": "What are the activities of requirement elicitation and Analysis? Explain.", + "unit": "Unit 2", + "type": "elicitation" + } + ] + }, + { + "id": "q4", + "questionNumber": "Q.4", + "subQuestions": [ + { + "id": "q4a", + "label": "a)", + "text": "Discuss about pattern based software design in detail?", + "unit": "Unit 3", + "type": "design-patterns" + }, + { + "id": "q4b", + "label": "b)", + "text": "Briefly explain about Function-Oriented design?", + "unit": "Unit 3", + "type": "function-oriented" + } + ] + }, + { + "id": "q5", + "questionNumber": "Q.5", + "subQuestions": [ + { + "id": "q5a", + "label": "a)", + "text": "List and explain the golden rules of User-Interface design?", + "unit": "Unit 3", + "type": "ui-design" + }, + { + "id": "q5b", + "label": "b)", + "text": "Briefly discuss about Integration testing Strategies?", + "unit": "Unit 4", + "type": "integration-testing" + } + ] + }, + { + "id": "q6", + "questionNumber": "Q.6", + "subQuestions": [ + { + "id": "q6a", + "label": "a)", + "text": "What is Black-Box testing? What is boundary value Analysis? Explain with example.", + "unit": "Unit 4", + "type": "black-box" + }, + { + "id": "q6b", + "label": "b)", + "text": "What is White-Box testing? How white box testing is carried out? Demonstrate with example.", + "unit": "Unit 4", + "type": "white-box" + } + ] + }, + { + "id": "q7", + "questionNumber": "Q.7", + "subQuestions": [ + { + "id": "q7a", + "label": "a)", + "text": "Explain briefly about Software Configuration Management (SCM)?", + "unit": "Unit 5", + "type": "scm" + }, + { + "id": "q7b", + "label": "b)", + "text": "What do you understand by Feasibility Analysis? Explain.", + "unit": "Unit 5", + "type": "feasibility" + } + ] + }, + { + "id": "q8", + "questionNumber": "Q.8", + "subQuestions": [ + { + "id": "q8", + "label": "", + "text": "Write short notes on any two: a) Schedule and Cost Estimation b) RUP c) Traceability d) Design Principles.", + "unit": "Unit 5/1/2/3", + "type": "mixed" + } + ] + } + ] + }, + { + "exam": "December 2024", + "year": 2024, + "month": "December", + "questions": [ + { + "id": "q1", + "questionNumber": "Q.1", + "subQuestions": [ + { + "id": "q1a", + "label": "a)", + "text": "Explain with neat diagram about RAD model.", + "unit": "Unit 1", + "type": "rad" + }, + { + "id": "q1b", + "label": "b)", + "text": "Describe briefly about Prototyping model for Software development?", + "unit": "Unit 1", + "type": "prototyping" + } + ] + }, + { + "id": "q2", + "questionNumber": "Q.2", + "subQuestions": [ + { + "id": "q2a", + "label": "a)", + "text": "Draw and explain the Incremental Model with its Merits and Demerits?", + "unit": "Unit 1", + "type": "incremental" + }, + { + "id": "q2b", + "label": "b)", + "text": "Discuss briefly about Use case Model with neat sketch?", + "unit": "Unit 2", + "type": "use-case" + } + ] + }, + { + "id": "q3", + "questionNumber": "Q.3", + "subQuestions": [ + { + "id": "q3a", + "label": "a)", + "text": "Differentiate between Function-Oriented and Object-Oriented Software development?", + "unit": "Unit 2", + "type": "analysis-modeling" + }, + { + "id": "q3b", + "label": "b)", + "text": "Describe different checks to be carried out during requirement validation process?", + "unit": "Unit 2", + "type": "validation" + } + ] + }, + { + "id": "q4", + "questionNumber": "Q.4", + "subQuestions": [ + { + "id": "q4a", + "label": "a)", + "text": "How system modeling is achieved using UML? Explain with a suitable example.", + "unit": "Unit 3", + "type": "uml" + }, + { + "id": "q4b", + "label": "b)", + "text": "What do you understand by Function-Oriented design? Discuss in detail.", + "unit": "Unit 3", + "type": "function-oriented" + } + ] + }, + { + "id": "q5", + "questionNumber": "Q.5", + "subQuestions": [ + { + "id": "q5a", + "label": "a)", + "text": "List and Explain different kinds of architecture styles and patterns?", + "unit": "Unit 3", + "type": "architectural-styles" + }, + { + "id": "q5b", + "label": "b)", + "text": "What is Test Oracles? Explain different types of test techniques.", + "unit": "Unit 4", + "type": "test-techniques" + } + ] + }, + { + "id": "q6", + "questionNumber": "Q.6", + "subQuestions": [ + { + "id": "q6a", + "label": "a)", + "text": "With neat sketch explain briefly about testing levels?", + "unit": "Unit 4", + "type": "testing-levels" + }, + { + "id": "q6b", + "label": "b)", + "text": "Explain briefly about Software Configuration Management (SCM)?", + "unit": "Unit 5", + "type": "scm" + } + ] + }, + { + "id": "q7", + "questionNumber": "Q.7", + "subQuestions": [ + { + "id": "q7a", + "label": "a)", + "text": "Discuss about Risk Assessment and Mitigation.", + "unit": "Unit 5", + "type": "risk" + }, + { + "id": "q7b", + "label": "b)", + "text": "What is Re-Engineering and discuss about steps involved in Re-Engineering?", + "unit": "Unit 5", + "type": "maintenance" + } + ] + }, + { + "id": "q8", + "questionNumber": "Q.8", + "subQuestions": [ + { + "id": "q8", + "label": "", + "text": "Write short notes on any two: i) Resource Allocation ii) Component Assembly Model iii) SA/SD Component Based Design iv) Testing frameworks.", + "unit": "Unit 5/1/3/4", + "type": "mixed" + } + ] + } + ] + }, + { + "exam": "June 2025", + "year": 2025, + "month": "June", + "questions": [ + { + "id": "q1", + "questionNumber": "Q.1", + "subQuestions": [ + { + "id": "q1a", + "label": "a)", + "text": "What are the five major activities of an operating system in regards to memory management?", + "unit": "Unit 1", + "type": "os" + }, + { + "id": "q1b", + "label": "b)", + "text": "List the functions of OS. How operating system perform management task in a system?", + "unit": "Unit 1", + "type": "os" + } + ] + }, + { + "id": "q2", + "questionNumber": "Q.2", + "subQuestions": [ + { + "id": "q2a", + "label": "a)", + "text": "What is the Component Assembly Model? How does it differ from the Incremental Model?", + "unit": "Unit 1", + "type": "process-models" + }, + { + "id": "q2b", + "label": "b)", + "text": "Explain the purpose of process customization and improvement with reference to CMM.", + "unit": "Unit 1", + "type": "cmm" + } + ] + }, + { + "id": "q3", + "questionNumber": "Q.3", + "subQuestions": [ + { + "id": "q3a", + "label": "a)", + "text": "Describe functional and non-functional requirements with examples.", + "unit": "Unit 2", + "type": "requirements" + }, + { + "id": "q3b", + "label": "b)", + "text": "What are the major requirement elicitation techniques? Discuss any two in detail.", + "unit": "Unit 2", + "type": "elicitation" + } + ] + }, + { + "id": "q4", + "questionNumber": "Q.4", + "subQuestions": [ + { + "id": "q4a", + "label": "a)", + "text": "Explain use case modeling with the help of an example.", + "unit": "Unit 2", + "type": "use-case" + }, + { + "id": "q4b", + "label": "b)", + "text": "What are the key contents of a Software Requirement Specification (SRS) document?", + "unit": "Unit 2", + "type": "srs" + } + ] + }, + { + "id": "q5", + "questionNumber": "Q.5", + "subQuestions": [ + { + "id": "q5a", + "label": "a)", + "text": "Describe any four fundamental software design principles.", + "unit": "Unit 3", + "type": "design-principles" + }, + { + "id": "q5b", + "label": "b)", + "text": "Explain the SA/SD approach to function-oriented design.", + "unit": "Unit 3", + "type": "sa-sd" + } + ] + }, + { + "id": "q6", + "questionNumber": "Q.6", + "subQuestions": [ + { + "id": "q6a", + "label": "a)", + "text": "What are architectural views? Briefly describe different architectural styles.", + "unit": "Unit 3", + "type": "architectural-views" + }, + { + "id": "q6b", + "label": "b)", + "text": "What are the key design metrics used to evaluate software design quality?", + "unit": "Unit 3", + "type": "design-metrics" + } + ] + }, + { + "id": "q7", + "questionNumber": "Q.7", + "subQuestions": [ + { + "id": "q7a", + "label": "a)", + "text": "Differentiate between static and dynamic code analysis.", + "unit": "Unit 4", + "type": "static-dynamic" + }, + { + "id": "q7b", + "label": "b)", + "text": "Describe the black-box testing technique with an example.", + "unit": "Unit 4", + "type": "black-box" + } + ] + }, + { + "id": "q8", + "questionNumber": "Q.8", + "subQuestions": [ + { + "id": "q8a", + "label": "a)", + "text": "What is Software Configuration Management (SCM)? Describe its major activities.", + "unit": "Unit 5", + "type": "scm" + }, + { + "id": "q8b", + "label": "b)", + "text": "Explain software project feasibility analysis and its types.", + "unit": "Unit 5", + "type": "feasibility" + } + ] + } + ] + } + ] } diff --git a/content/rgpv/cse/semester-4/cs-403/syllabus.json b/content/rgpv/cse/semester-4/cs-403/syllabus.json index b40e4f4..1284637 100644 --- a/content/rgpv/cse/semester-4/cs-403/syllabus.json +++ b/content/rgpv/cse/semester-4/cs-403/syllabus.json @@ -3,107 +3,425 @@ "id": "cs-403", "code": "CS-403", "name": "Software Engineering", - "title": "CS-403 - Software Engineering", - "semester": "IV" + "title": "CS-403 – Software Engineering (SE)", + "university": "Rajiv Gandhi Proudyogiki Vishwavidyalaya, Bhopal", + "scheme": "New Scheme Based On AICTE Flexible Curricula", + "semester": "IV", + "branch": "CSE-Computer Science Engineering" }, "modules": [ { - "id": "module-1", + "id": "cs403-m1", "number": 1, "title": "The Software Product and Software Process", - "hours": 8, + "hours": null, "topics": [ - "Software Product and Process Characteristics", - "Software Process Models: Linear Sequential Model, Prototyping Model, RAD Model", - "Evolutionary Process Models like Incremental Model, Spiral Model", - "Component Assembly Model", - "RUP and Agile processes", - "Software Process customization and improvement", - "CMM", - "Product and ProcessMetrics" - ] + { + "id": "cs403-m1-product-process", + "slug": "software-product-process", + "title": "Software Product and Process Characteristics", + "displayOrder": 1 + }, + { + "id": "cs403-m1-linear-sequential", + "slug": "linear-sequential-model", + "title": "Linear Sequential Model", + "displayOrder": 2 + }, + { + "id": "cs403-m1-prototyping", + "slug": "prototyping-model", + "title": "Prototyping Model", + "displayOrder": 3 + }, + { + "id": "cs403-m1-rad", + "slug": "rad-model", + "title": "RAD Model", + "displayOrder": 4 + }, + { + "id": "cs403-m1-evolutionary", + "slug": "evolutionary-process-models", + "title": "Evolutionary Process Models (Incremental Model, Spiral Model, Component Assembly Model)", + "displayOrder": 5 + }, + { + "id": "cs403-m1-rup-agile", + "slug": "rup-agile-processes", + "title": "RUP and Agile processes", + "displayOrder": 6 + }, + { + "id": "cs403-m1-cmm", + "slug": "cmm", + "title": "Software Process customization and improvement, CMM", + "displayOrder": 7 + }, + { + "id": "cs403-m1-metrics", + "slug": "product-process-metrics", + "title": "Product and Process Metrics", + "displayOrder": 8 + } + ], + "questionIds": [ + "cs403_m1_june2025_q1", + "cs403_m1_june2025_q2", + "cs403_m1_june2025_q3", + "cs403_m1_june2025_q4", + "cs403_m1_dec2024_q5", + "cs403_m1_dec2024_q6", + "cs403_m1_dec2024_q7", + "cs403_m1_june2024_q8", + "cs403_m1_june2024_q9", + "cs403_m1_june2024_q10", + "cs403_m1_june2024_q11", + "cs403_m1_nov2023_q12", + "cs403_m1_nov2023_q13", + "cs403_m1_nov2023_q14", + "cs403_m1_nov2023_q15", + "cs403_m1_june2023_q16", + "cs403_m1_june2023_q17", + "cs403_m1_june2023_q18", + "cs403_m1_nov2022_q19", + "cs403_m1_nov2022_q20", + "cs403_m1_nov2022_q21" + ], + "predictedQuestionIds": [] }, { - "id": "module-2", + "id": "cs403-m2", "number": 2, "title": "Requirement Elicitation, Analysis, and Specification", - "hours": 8, + "hours": null, "topics": [ - "Functional and Non-functional requirements", - "Requirement Sources and Elicitation Techniques", - "Analysis Modeling for Function-oriented and Object-oriented software development", - "Use case Modeling", - "System and Software Requirement Specifications", - "Requirement Validation", - "Traceability" - ] + { + "id": "cs403-m2-functional-nonfunctional", + "slug": "functional-nonfunctional-requirements", + "title": "Functional and Non-functional requirements", + "displayOrder": 1 + }, + { + "id": "cs403-m2-elicitation", + "slug": "requirement-elicitation", + "title": "Requirement Sources and Elicitation Techniques", + "displayOrder": 2 + }, + { + "id": "cs403-m2-analysis-modeling", + "slug": "analysis-modeling", + "title": "Analysis Modeling for Function-oriented and Object-oriented software development", + "displayOrder": 3 + }, + { + "id": "cs403-m2-use-case", + "slug": "use-case-modeling", + "title": "Use case Modeling", + "displayOrder": 4 + }, + { + "id": "cs403-m2-srs", + "slug": "srs", + "title": "System and Software Requirement Specifications", + "displayOrder": 5 + }, + { + "id": "cs403-m2-validation", + "slug": "requirement-validation", + "title": "Requirement Validation", + "displayOrder": 6 + }, + { + "id": "cs403-m2-traceability", + "slug": "traceability", + "title": "Traceability", + "displayOrder": 7 + } + ], + "questionIds": [ + "cs403_m2_june2025_q1", + "cs403_m2_june2025_q2", + "cs403_m2_june2025_q3", + "cs403_m2_june2025_q4", + "cs403_m2_dec2024_q5", + "cs403_m2_dec2024_q6", + "cs403_m2_dec2024_q7", + "cs403_m2_june2024_q8", + "cs403_m2_june2024_q9", + "cs403_m2_june2024_q10", + "cs403_m2_june2024_q11", + "cs403_m2_nov2023_q11", + "cs403_m2_nov2023_q12", + "cs403_m2_nov2023_q13", + "cs403_m2_june2023_q14", + "cs403_m2_june2023_q15", + "cs403_m2_june2023_q16", + "cs403_m2_nov2022_q11", + "cs403_m2_nov2022_q17", + "cs403_m2_nov2022_q18" + ], + "predictedQuestionIds": [] }, { - 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"id": "module-4", + "id": "cs403-m4", "number": 4, "title": "Software Analysis and Testing", - "hours": 8, + "hours": null, "topics": [ - "Software Static and Dynamic analysis", - "Code inspections", - "Software Testing, Fundamentals", - "Software Test Process", - "Testing Levels", - "Test Criteria", - "Test Case Design", - "Test Oracles", - "Test Techniques", - "BlackBox Testing", - "White-Box Unit Testing and Unit", - "Testing Frameworks", - "Integration Testing", - "System Testing and other Specialized Testing", - "Test Plan, Test Metrics, Testing Tools", - "Introduction to Object-oriented analysis, design and comparison with structured SoftwareEngg" - ] + { + "id": "cs403-m4-static-dynamic", + "slug": "static-dynamic-analysis", + "title": "Software Static and Dynamic analysis, Code inspections", + "displayOrder": 1 + }, + { + "id": "cs403-m4-testing-fundamentals", + "slug": "software-testing-fundamentals", + "title": "Software Testing Fundamentals, Software Test Process", + "displayOrder": 2 + }, + { + "id": "cs403-m4-testing-levels", + "slug": "testing-levels", + "title": "Testing Levels, Test Criteria", + "displayOrder": 3 + }, + { + "id": "cs403-m4-test-case", + "slug": "test-case-design", + "title": "Test Case Design, Test Oracles, Test Techniques", + "displayOrder": 4 + }, + { + "id": "cs403-m4-black-box", + "slug": "black-box-testing", + "title": "Black-Box Testing", + "displayOrder": 5 + }, + { + "id": "cs403-m4-white-box", + "slug": "white-box-testing", + "title": "White-Box Unit Testing and Unit Testing Frameworks", + "displayOrder": 6 + }, + { + "id": "cs403-m4-integration", + "slug": "integration-system-testing", + "title": "Integration Testing, System Testing and other Specialized Testing", + "displayOrder": 7 + }, + { + "id": "cs403-m4-test-plan", + "slug": "test-plan-metrics", + "title": "Test Plan, Test Metrics, Testing Tools", + "displayOrder": 8 + }, + { + "id": "cs403-m4-oo-analysis", + "slug": "object-oriented-analysis", + "title": "Introduction to Object-oriented analysis, design and comparison with structured SE", + "displayOrder": 9 + } + ], + "questionIds": [ + "cs403_m4_june2025_q1", + "cs403_m4_june2025_q2", + "cs403_m4_dec2024_q3", + "cs403_m4_dec2024_q4", + "cs403_m4_dec2024_q5", + "cs403_m4_june2024_q6", + "cs403_m4_june2024_q7", + "cs403_m4_june2024_q8", + "cs403_m4_nov2023_q9", + "cs403_m4_nov2023_q10", + "cs403_m4_nov2023_q11", + "cs403_m4_nov2023_q12", + "cs403_m4_nov2023_q13", + "cs403_m4_june2023_q14", + "cs403_m4_june2023_q15", + "cs403_m4_june2023_q16", + "cs403_m4_june2023_q17", + "cs403_m4_june2023_q18", + "cs403_m4_june2023_q19", + "cs403_m4_nov2022_q20", + "cs403_m4_nov2022_q21", + "cs403_m4_nov2022_q22", + "cs403_m4_nov2022_q23" + ], + "predictedQuestionIds": [] }, { - "id": "module-5", + "id": "cs403-m5", "number": 5, "title": "Software Maintenance & Software Project Measurement", - "hours": 8, + "hours": null, "topics": [ - "Need and Types of Maintenance", - "Software Configuration Management (SCM)", - "Software Change Management", - "Version Control", - "Change control and Reporting", - "Program Comprehension Techniques", - "Re-engineering", - "Reverse Engineering", - "Tool Support", - "Project Management Concepts", - "Feasibility Analysis", - "Project and Process Planning", - "Resources Allocations", - "Software efforts, Schedule, and Cost estimations", - "Project Scheduling and Tracking", - "Risk Assessment and Mitigation", - "Software Quality Assurance (SQA)", - "Project Plan, ProjectMetrics" - ] + { + "id": "cs403-m5-maintenance", + "slug": "software-maintenance", + "title": "Need and Types of Maintenance", + "displayOrder": 1 + }, + { + "id": "cs403-m5-scm", + "slug": "scm", + "title": "Software Configuration Management (SCM), Software Change Management, Version Control, Change control and Reporting", + "displayOrder": 2 + }, + { + "id": "cs403-m5-comprehension", + "slug": "program-comprehension", + "title": "Program Comprehension Techniques", + "displayOrder": 3 + }, + { + "id": "cs403-m5-reengineering", + "slug": "reengineering-reverse-engineering", + "title": "Re-engineering, Reverse Engineering, Tool Support", + "displayOrder": 4 + }, + { + "id": "cs403-m5-project-management", + "slug": "project-management", + "title": "Project Management Concepts, Feasibility Analysis, Project and Process Planning, Resources Allocations", + "displayOrder": 5 + }, + { + "id": "cs403-m5-estimation", + "slug": "effort-schedule-cost", + "title": "Software efforts, Schedule, and Cost estimations", + "displayOrder": 6 + }, + { + "id": "cs403-m5-scheduling", + "slug": "project-scheduling-tracking", + "title": "Project Scheduling and Tracking", + "displayOrder": 7 + }, + { + "id": "cs403-m5-risk", + "slug": "risk-assessment-mitigation", + "title": "Risk Assessment and Mitigation", + "displayOrder": 8 + }, + { + "id": "cs403-m5-sqa", + "slug": "sqa", + "title": "Software Quality Assurance (SQA)", + "displayOrder": 9 + }, + { + "id": "cs403-m5-project-plan", + "slug": "project-plan-metrics", + "title": "Project Plan, Project Metrics", + "displayOrder": 10 + } + ], + "questionIds": [ + "cs403_m5_june2025_q1", + "cs403_m5_june2025_q2", + "cs403_m5_june2024_q3", + "cs403_m5_dec2024_q3", + "cs403_m5_dec2024_q4", + "cs403_m5_dec2024_q5", + "cs403_m5_dec2024_q6", + "cs403_m5_june2024_q7", + "cs403_m5_june2024_q8", + "cs403_m5_nov2023_q9", + "cs403_m5_nov2023_q10", + "cs403_m5_nov2023_q11", + "cs403_m5_nov2023_q12", + "cs403_m5_nov2023_q13", + "cs403_m5_june2023_q14", + "cs403_m5_june2023_q15", + "cs403_m5_june2023_q16", + "cs403_m5_nov2022_q17", + "cs403_m5_nov2022_q18", + "cs403_m5_nov2022_q19" + ], + "predictedQuestionIds": [] } ] } diff --git a/content/rgpv/cse/semester-4/cs-404/pyqs.json b/content/rgpv/cse/semester-4/cs-404/pyqs.json index d508159..691438f 100644 --- a/content/rgpv/cse/semester-4/cs-404/pyqs.json +++ b/content/rgpv/cse/semester-4/cs-404/pyqs.json @@ -2,8 +2,970 @@ "subject": { "id": "cs-404", "code": "CS-404", - "name": "Computer Org. & Architecture (COA)", - "title": "CS-404 - Computer Org. & Architecture (COA)" + "name": "Computer Organization & Architecture", + "title": "AL/CSIT (CI)/CS/CT/CO/IO/IS-404 (GS) – Computer Organization & Architecture", + "semester": "IV", + "gradingSystem": "Grading System (GS)", + "maxMarks": 70, + "time": "3 Hours", + "commonInstructions": [ + "Attempt any five questions.", + "All questions carry equal marks." + ] }, - "papers": [] + "papers": [ + { + "exam": "November 2022", + "year": 2022, + "month": "November", + "questions": [ + { + "id": "q1", + "questionNumber": "Q.1", + "subQuestions": [ + { + "id": "q1a", + "label": "a)", + "text": "Briefly explain the addressing modes in detail.", + "unit": "Unit 1", + "type": "addressing-modes" + }, + { + "id": "q1b", + "label": "b)", + "text": "Discuss Stack Organization in detail.", + "unit": "Unit 1", + "type": "stack" + } + ] + }, + { + "id": "q2", + "questionNumber": "Q.2", + "subQuestions": [ + { + "id": "q2a", + "label": "a)", + "text": "What is Arithmetic operation? Explain how negative numbers are represented in 2's complement form?", + "unit": "Unit 3", + "type": "arithmetic" + }, + { + "id": "q2b", + "label": "b)", + "text": "Discuss Binary Addition. Explain the concept of Half Adder and Full Adder.", + "unit": "Unit 3", + "type": "arithmetic" + } + ] + }, + { + "id": "q3", + "questionNumber": "Q.3", + "subQuestions": [ + { + "id": "q3a", + "label": "a)", + "text": "Write a short note on Direct Memory Access (DMA).", + "unit": "Unit 4", + "type": "dma" + }, + { + "id": "q3b", + "label": "b)", + "text": "Explain serial and parallel data transfer techniques in detail.", + "unit": "Unit 4", + "type": "data-transfer" + } + ] + }, + { + "id": "q4", + "questionNumber": "Q.4", + "subQuestions": [ + { + "id": "q4", + "label": "", + "text": "What is Cache mapping? Explain all cache mapping techniques in detail.", + "unit": "Unit 5", + "type": "cache" + } + ] + }, + { + "id": "q5", + "questionNumber": "Q.5", + "subQuestions": [ + { + "id": "q5a", + "label": "a)", + "text": "Write a short note on AMD processor.", + "unit": "Unit 6", + "type": "processor" + }, + { + "id": "q5b", + "label": "b)", + "text": "Explain the difference between Single and Multi-processor System.", + "unit": "Unit 6", + "type": "multiprocessor" + } + ] + }, + { + "id": "q6", + "questionNumber": "Q.6", + "subQuestions": [ + { + "id": "q6", + "label": "", + "text": "Discuss: a) CISC Architecture b) Magnetic Tape.", + "unit": "Unit 6/5", + "type": "mixed" + } + ] + }, + { + "id": "q7", + "questionNumber": "Q.7", + "subQuestions": [ + { + "id": "q7", + "label": "", + "text": "Write short notes on: a) Hit Ratio b) Average Access Time.", + "unit": "Unit 5", + "type": "cache" + } + ] + }, + { + "id": "q8", + "questionNumber": "Q.8", + "subQuestions": [ + { + "id": "q8", + "label": "", + "text": "Briefly explain Hardwired and Micro-programmed control unit.", + "unit": "Unit 2", + "type": "control-unit" + } + ] + } + ] + }, + { + "exam": "June 2023", + "year": 2023, + "month": "June", + "questions": [ + { + "id": "q1", + "questionNumber": "Q.1", + "subQuestions": [ + { + "id": "q1a", + "label": "a)", + "text": "Explain basic principles of computer architecture.", + "unit": "Unit 1", + "type": "architecture" + }, + { + "id": "q1b", + "label": "b)", + "text": "What is Multiprocessing? Discuss types of data transfer in detail.", + "unit": "Unit 4", + "type": "multiprocessing" + } + ] + }, + { + "id": "q2", + "questionNumber": "Q.2", + "subQuestions": [ + { + "id": "q2a", + "label": "a)", + "text": "Explain: i) Stack organization ii) Bus structure and addressing modes iii) Fetch and execution cycle.", + "unit": "Unit 1", + "type": "basics" + }, + { + "id": "q2b", + "label": "b)", + "text": "Discuss instruction types and explain execution of micro instruction.", + "unit": "Unit 2", + "type": "control-unit" + } + ] + }, + { + "id": "q3", + "questionNumber": "Q.3", + "subQuestions": [ + { + "id": "q3a", + "label": "a)", + "text": "Write Booths algorithm. Also explain floating point arithmetic operation.", + "unit": "Unit 3", + "type": "arithmetic" + }, + { + "id": "q3b", + "label": "b)", + "text": "Describe signal addition and subtraction in detail.", + "unit": "Unit 3", + "type": "arithmetic" + } + ] + }, + { + "id": "q4", + "questionNumber": "Q.4", + "subQuestions": [ + { + "id": "q4a", + "label": "a)", + "text": "Elaborate: i) Serial and parallel data transfer ii) Synchronous and asynchronous modes of data transfer.", + "unit": "Unit 4", + "type": "data-transfer" + }, + { + "id": "q4b", + "label": "b)", + "text": "Write notes on: i) Direct memory access ii) PCI Bus and SCSI Bus.", + "unit": "Unit 4", + "type": "dma" + } + ] + }, + { + "id": "q5", + "questionNumber": "Q.5", + "subQuestions": [ + { + "id": "q5a", + "label": "a)", + "text": "Compare: i) Main memory and secondary memory ii) Cache memory and Virtual memory.", + "unit": "Unit 5", + "type": "memory" + }, + { + "id": "q5b", + "label": "b)", + "text": "Describe replacement algorithm and write steps to improve cache performance.", + "unit": "Unit 5", + "type": "cache" + } + ] + }, + { + "id": "q6", + "questionNumber": "Q.6", + "subQuestions": [ + { + "id": "q6a", + "label": "a)", + "text": "Explain characteristics and structure of multiprocessor.", + "unit": "Unit 6", + "type": "multiprocessor" + }, + { + "id": "q6b", + "label": "b)", + "text": "What is concept of pipelining? Differentiate vector processing and array processing.", + "unit": "Unit 6", + "type": "pipelining" + } + ] + }, + { + "id": "q7", + "questionNumber": "Q.7", + "subQuestions": [ + { + "id": "q7a", + "label": "a)", + "text": "Describe: i) LRU algorithm ii) Two's complement representation iii) Memory management hardware.", + "unit": "Unit 5", + "type": "memory" + }, + { + "id": "q7b", + "label": "b)", + "text": "What is inter-processor communication and synchronization? Also describe inter-processor arbitration.", + "unit": "Unit 6", + "type": "multiprocessor" + } + ] + }, + { + "id": "q8", + "questionNumber": "Q.8", + "subQuestions": [ + { + "id": "q8a", + "label": "a)", + "text": "Discuss multicore processor in detail.", + "unit": "Unit 6", + "type": "multicore" + }, + { + "id": "q8b", + "label": "b)", + "text": "Write short notes on: i) Semiconductor memories ii) Hardwired control unit iii) RISC and CISC iv) Micro instruction formats.", + "unit": "Unit 2", + "type": "mixed" + } + ] + } + ] + }, + { + "exam": "November 2023", + "year": 2023, + "month": "November", + "questions": [ + { + "id": "q1", + "questionNumber": "Q.1", + "subQuestions": [ + { + "id": "q1a", + "label": "a)", + "text": "Draw and explain the architecture of a computer system.", + "unit": "Unit 1", + "type": "architecture" + }, + { + "id": "q1b", + "label": "b)", + "text": "Explain the addressing modes with suitable examples.", + "unit": "Unit 1", + "type": "addressing-modes" + } + ] + }, + { + "id": "q2", + "questionNumber": "Q.2", + "subQuestions": [ + { + "id": "q2a", + "label": "a)", + "text": "Discuss the Booth's algorithm for multiplication of signed numbers.", + "unit": "Unit 3", + "type": "arithmetic" + }, + { + "id": "q2b", + "label": "b)", + "text": "What do you understand by direct memory access? Explain with block diagram how DMA operation is carried out.", + "unit": "Unit 4", + "type": "dma" + } + ] + }, + { + "id": "q3", + "questionNumber": "Q.3", + "subQuestions": [ + { + "id": "q3a", + "label": "a)", + "text": "Explain the concept of pipelining.", + "unit": "Unit 6", + "type": "pipelining" + }, + { + "id": "q3b", + "label": "b)", + "text": "Differentiate between vectored and non-vectored interrupts.", + "unit": "Unit 4", + "type": "interrupts" + } + ] + }, + { + "id": "q4", + "questionNumber": "Q.4", + "subQuestions": [ + { + "id": "q4a", + "label": "a)", + "text": "Explain the instruction formats for computer system.", + "unit": "Unit 1", + "type": "instruction-format" + }, + { + "id": "q4b", + "label": "b)", + "text": "List the differences between volatile and non-volatile memories?", + "unit": "Unit 5", + "type": "memory" + } + ] + }, + { + "id": "q5", + "questionNumber": "Q.5", + "subQuestions": [ + { + "id": "q5a", + "label": "a)", + "text": "Discuss memory hierarchy in computer system.", + "unit": "Unit 5", + "type": "memory" + }, + { + "id": "q5b", + "label": "b)", + "text": "Explain the mapping techniques in cache memory.", + "unit": "Unit 5", + "type": "cache" + } + ] + }, + { + "id": "q6", + "questionNumber": "Q.6", + "subQuestions": [ + { + "id": "q6a", + "label": "a)", + "text": "Explain: i) Cache hit and Cache miss ii) Cache coherency.", + "unit": "Unit 5", + "type": "cache" + }, + { + "id": "q6b", + "label": "b)", + "text": "Write short notes on the USB interface.", + "unit": "Unit 4", + "type": "io" + } + ] + }, + { + "id": "q7", + "questionNumber": "Q.7", + "subQuestions": [ + { + "id": "q7a", + "label": "a)", + "text": "Explain RISC Vs CISC.", + "unit": "Unit 6", + "type": "risc-cisc" + }, + { + "id": "q7b", + "label": "b)", + "text": "Explain Micro-program sequencer.", + "unit": "Unit 2", + "type": "control-unit" + } + ] + }, + { + "id": "q8", + "questionNumber": "Q.8", + "subQuestions": [ + { + "id": "q8a", + "label": "a)", + "text": "What is memory organization? Discuss the different types of memory organization in computer system.", + "unit": "Unit 5", + "type": "memory" + }, + { + "id": "q8b", + "label": "b)", + "text": "Explain the PCI, BUS and LRU algorithm in briefly.", + "unit": "Unit 4", + "type": "io" + } + ] + } + ] + }, + { + "exam": "June 2024", + "year": 2024, + "month": "June", + "questions": [ + { + "id": "q1", + "questionNumber": "Q.1", + "subQuestions": [ + { + "id": "q1a", + "label": "a)", + "text": "Explain the role and significance of registers in a CPU's general register organization.", + "unit": "Unit 1", + "type": "registers" + }, + { + "id": "q1b", + "label": "b)", + "text": "Differentiate between Hardwired control unit and Micro-programmed control unit.", + "unit": "Unit 2", + "type": "control-unit" + } + ] + }, + { + "id": "q2", + "questionNumber": "Q.2", + "subQuestions": [ + { + "id": "q2a", + "label": "a)", + "text": "What is register transfer language? Explain representation of instructions in RTL with suitable examples.", + "unit": "Unit 1", + "type": "rtl" + }, + { + "id": "q2b", + "label": "b)", + "text": "Discuss how two's complement is used for representing negative numbers and performing subtraction as addition with complement.", + "unit": "Unit 3", + "type": "arithmetic" + } + ] + }, + { + "id": "q3", + "questionNumber": "Q.3", + "subQuestions": [ + { + "id": "q3a", + "label": "a)", + "text": "Discuss how binary division is performed and the steps involved with flowchart.", + "unit": "Unit 3", + "type": "arithmetic" + }, + { + "id": "q3b", + "label": "b)", + "text": "Design a 4-bit adder/subtractor circuit and explain how addition and subtraction are performed.", + "unit": "Unit 3", + "type": "arithmetic" + } + ] + }, + { + "id": "q4", + "questionNumber": "Q.4", + "subQuestions": [ + { + "id": "q4a", + "label": "a)", + "text": "Why interface is needed in input output device? Explain how it is connected to I/O devices with neat sketch.", + "unit": "Unit 4", + "type": "io" + }, + { + "id": "q4b", + "label": "b)", + "text": "Describe the strobe control and hand shaking methods in asynchronous data transfer.", + "unit": "Unit 4", + "type": "data-transfer" + } + ] + }, + { + "id": "q5", + "questionNumber": "Q.5", + "subQuestions": [ + { + "id": "q5a", + "label": "a)", + "text": "What is the need of I/O processor? Explain the working of I/O processor.", + "unit": "Unit 4", + "type": "io" + }, + { + "id": "q5b", + "label": "b)", + "text": "Discuss different types of secondary memory devices (HDDs, magnetic tapes, optical discs). Compare advantages and disadvantages.", + "unit": "Unit 5", + "type": "memory" + } + ] + }, + { + "id": "q6", + "questionNumber": "Q.6", + "subQuestions": [ + { + "id": "q6a", + "label": "a)", + "text": "Define cache memory and explain its role in improving CPU performance. Discuss principles of locality.", + "unit": "Unit 5", + "type": "cache" + }, + { + "id": "q6b", + "label": "b)", + "text": "Describe the role of MMU in a computer system. Explain address translation between virtual and physical addresses.", + "unit": "Unit 5", + "type": "memory" + } + ] + }, + { + "id": "q7", + "questionNumber": "Q.7", + "subQuestions": [ + { + "id": "q7a", + "label": "a)", + "text": "Define RISC and CISC architectures and explain their fundamental differences.", + "unit": "Unit 6", + "type": "risc-cisc" + }, + { + "id": "q7b", + "label": "b)", + "text": "Discuss how pipelining improves instruction execution throughput and overall system performance.", + "unit": "Unit 6", + "type": "pipelining" + } + ] + }, + { + "id": "q8", + "questionNumber": "Q.8", + "subQuestions": [ + { + "id": "q8", + "label": "", + "text": "Write short notes on any two: a) Bus structure b) SCSI Bus c) Random Access Memory d) Inter processor arbitration.", + "unit": "Unit 1/4/5/6", + "type": "mixed" + } + ] + } + ] + }, + { + "exam": "December 2024", + "year": 2024, + "month": "December", + "questions": [ + { + "id": "q1", + "questionNumber": "Q.1", + "subQuestions": [ + { + "id": "q1a", + "label": "a)", + "text": "Differentiate between accumulator, index, stack and general-purpose registers in terms of their functions and usage.", + "unit": "Unit 1", + "type": "registers" + }, + { + "id": "q1b", + "label": "b)", + "text": "Discuss the sequence of steps involved in fetching an instruction from memory and executing it.", + "unit": "Unit 2", + "type": "control-unit" + } + ] + }, + { + "id": "q2", + "questionNumber": "Q.2", + "subQuestions": [ + { + "id": "q2a", + "label": "a)", + "text": "Describe how micro instructions are arranged in control memory and how they are interpreted.", + "unit": "Unit 2", + "type": "control-unit" + }, + { + "id": "q2b", + "label": "b)", + "text": "Draw flowchart for Booth's algorithm for multiplication of signed 2's complement numbers and explain with example.", + "unit": "Unit 3", + "type": "arithmetic" + } + ] + }, + { + "id": "q3", + "questionNumber": "Q.3", + "subQuestions": [ + { + "id": "q3a", + "label": "a)", + "text": "Describe basic arithmetic operations supported by floating-point arithmetic including addition, subtraction, multiplication and division.", + "unit": "Unit 3", + "type": "arithmetic" + }, + { + "id": "q3b", + "label": "b)", + "text": "What components are required to design the arithmetic unit? Explain with neat sketch.", + "unit": "Unit 3", + "type": "arithmetic" + } + ] + }, + { + "id": "q4", + "questionNumber": "Q.4", + "subQuestions": [ + { + "id": "q4a", + "label": "a)", + "text": "Discuss fundamental differences between serial and parallel data transfer methods in terms of data transmission, speed and implementation complexity.", + "unit": "Unit 4", + "type": "data-transfer" + }, + { + "id": "q4b", + "label": "b)", + "text": "What is direct memory transfer? Give an overview and block diagram of a DMA controller.", + "unit": "Unit 4", + "type": "dma" + } + ] + }, + { + "id": "q5", + "questionNumber": "Q.5", + "subQuestions": [ + { + "id": "q5a", + "label": "a)", + "text": "Differentiate synchronous and asynchronous data transfer.", + "unit": "Unit 4", + "type": "data-transfer" + }, + { + "id": "q5b", + "label": "b)", + "text": "Explain the concept of memory hierarchy and its significance in modern computer systems.", + "unit": "Unit 5", + "type": "memory" + } + ] + }, + { + "id": "q6", + "questionNumber": "Q.6", + "subQuestions": [ + { + "id": "q6a", + "label": "a)", + "text": "Compare and contrast different cache mapping techniques: direct mapping, set-associative and fully associative. Discuss advantages and disadvantages.", + "unit": "Unit 5", + "type": "cache" + }, + { + "id": "q6b", + "label": "b)", + "text": "Explain memory segmentation and how it complements virtual memory. Discuss advantages and challenges.", + "unit": "Unit 5", + "type": "memory" + } + ] + }, + { + "id": "q7", + "questionNumber": "Q.7", + "subQuestions": [ + { + "id": "q7a", + "label": "a)", + "text": "Describe different types of interconnection networks used in multiprocessor systems.", + "unit": "Unit 6", + "type": "multiprocessor" + }, + { + "id": "q7b", + "label": "b)", + "text": "Define array processing and explain its significance in computer architecture and parallel computing.", + "unit": "Unit 6", + "type": "array-processing" + } + ] + }, + { + "id": "q8", + "questionNumber": "Q.8", + "subQuestions": [ + { + "id": "q8", + "label": "", + "text": "Write short notes on any two: a) Instruction types b) PCI Bus c) Read Only Memory d) Inter-processor communication and synchronization.", + "unit": "Unit 2/4/5/6", + "type": "mixed" + } + ] + } + ] + }, + { + "exam": "June 2025", + "year": 2025, + "month": "June", + "questions": [ + { + "id": "q1", + "questionNumber": "Q.1", + "subQuestions": [ + { + "id": "q1a", + "label": "a)", + "text": "Discuss the structure and role of program counter, instruction register and memory register during a fetch-execute cycle.", + "unit": "Unit 2", + "type": "control-unit" + }, + { + "id": "q1b", + "label": "b)", + "text": "How does the control word help in micro-operation execution? Illustrate with an example.", + "unit": "Unit 1", + "type": "micro-operations" + } + ] + }, + { + "id": "q2", + "questionNumber": "Q.2", + "subQuestions": [ + { + "id": "q2a", + "label": "a)", + "text": "Illustrate the concept of bus structure. How does it aid in CPU and memory communication?", + "unit": "Unit 1", + "type": "bus" + }, + { + "id": "q2b", + "label": "b)", + "text": "Explain 1's and 2's complement representation for negative numbers with examples.", + "unit": "Unit 3", + "type": "arithmetic" + } + ] + }, + { + "id": "q3", + "questionNumber": "Q.3", + "subQuestions": [ + { + "id": "q3a", + "label": "a)", + "text": "Describe Booth's algorithm for multiplication. Illustrate with a 4-bit example.", + "unit": "Unit 3", + "type": "arithmetic" + }, + { + "id": "q3b", + "label": "b)", + "text": "Compare fixed point and floating point arithmetic operations with examples.", + "unit": "Unit 3", + "type": "arithmetic" + } + ] + }, + { + "id": "q4", + "questionNumber": "Q.4", + "subQuestions": [ + { + "id": "q4a", + "label": "a)", + "text": "How does USB differ from SCSI bus in terms of speed, cost and application?", + "unit": "Unit 4", + "type": "io" + }, + { + "id": "q4b", + "label": "b)", + "text": "Write a comparative note on different types of I/O interfaces.", + "unit": "Unit 4", + "type": "io" + } + ] + }, + { + "id": "q5", + "questionNumber": "Q.5", + "subQuestions": [ + { + "id": "q5a", + "label": "a)", + "text": "Explain the working of PCI bus. How does it improve I/O performance?", + "unit": "Unit 4", + "type": "io" + }, + { + "id": "q5b", + "label": "b)", + "text": "Differentiate magnetic tape, disk and optical storage based on access time, reliability and cost.", + "unit": "Unit 5", + "type": "memory" + } + ] + }, + { + "id": "q6", + "questionNumber": "Q.6", + "subQuestions": [ + { + "id": "q6a", + "label": "a)", + "text": "How does cache memory improve system performance? Explain cache design.", + "unit": "Unit 5", + "type": "cache" + }, + { + "id": "q6b", + "label": "b)", + "text": "Write a program in Pseudo code to simulate page replacement using LRU.", + "unit": "Unit 5", + "type": "memory" + } + ] + }, + { + "id": "q7", + "questionNumber": "Q.7", + "subQuestions": [ + { + "id": "q7a", + "label": "a)", + "text": "Describe the structure and working of inter-processor communication and synchronization.", + "unit": "Unit 5", + "type": "multiprocessor" + }, + { + "id": "q7b", + "label": "b)", + "text": "Compare RISC and CISC architectures with examples.", + "unit": "Unit 5", + "type": "risc-cisc" + } + ] + }, + { + "id": "q8", + "questionNumber": "Q.8", + "subQuestions": [ + { + "id": "q8", + "label": "", + "text": "Write short notes on any two: a) Direct Memory Access b) Virtual Memory c) Read Only Memory.", + "unit": "Unit 4/5", + "type": "mixed" + } + ] + } + ] + } + ] } diff --git a/content/rgpv/cse/semester-4/cs-404/syllabus.json b/content/rgpv/cse/semester-4/cs-404/syllabus.json index 8124271..3d6c5e7 100644 --- a/content/rgpv/cse/semester-4/cs-404/syllabus.json +++ b/content/rgpv/cse/semester-4/cs-404/syllabus.json @@ -3,100 +3,403 @@ "id": "cs-404", "code": "CS-404", "name": "Computer Org. & Architecture", - "title": "CS-404 - Computer Org. & Architecture", - "semester": "IV" + "title": "CS-404 – Computer Org. & Architecture (COA)", + "university": "Rajiv Gandhi Proudyogiki Vishwavidyalaya, Bhopal", + "scheme": "New Scheme Based On AICTE Flexible Curricula", + "semester": "IV", + "branch": "CSE-Computer Science Engineering" }, "modules": [ { - "id": "module-1", + "id": "cs404-m1", "number": 1, "title": "Basic Structure of Computer", - "hours": 8, + "hours": null, "topics": [ - "Structure of Desktop Computers", - "CPU: General Register Organization-Memory Register, Instruction Register, Control Word, Stack Organization", - "Instruction Format", - "ALU", - "I/O System", - "bus", - "CPU and Memory Program Counter", - "Bus Structure", - "Register Transfer Language-Bus and Memory Transfer", - "addressing modes" - ] + { + "id": "cs404-m1-desktop-structure", + "slug": "desktop-structure", + "title": "Structure of Desktop Computers", + "displayOrder": 1 + }, + { + "id": "cs404-m1-cpu-registers", + "slug": "cpu-general-register-organization", + "title": "CPU: General Register Organization-Memory Register, Instruction Register, Control Word", + "displayOrder": 2 + }, + { + "id": "cs404-m1-stack-org", + "slug": "stack-organization", + "title": "Stack Organization", + "displayOrder": 3 + }, + { + "id": "cs404-m1-instruction-format", + "slug": "instruction-format", + "title": "Instruction Format", + "displayOrder": 4 + }, + { + "id": "cs404-m1-alu-io", + "slug": "alu-io-system-bus", + "title": "ALU, I/O System, bus", + "displayOrder": 5 + }, + { + "id": "cs404-m1-pc-bus-rtl", + "slug": "cpu-memory-pc-bus-rtl", + "title": "CPU and Memory Program Counter, Bus Structure, Register Transfer Language-Bus and Memory Transfer", + "displayOrder": 6 + }, + { + "id": "cs404-m1-addressing-modes", + "slug": "addressing-modes", + "title": "Addressing modes", + "displayOrder": 7 + } + ], + "questionIds": [ + "cs404_m1_june2025_q1", + "cs404_m1_june2025_q2", + "cs404_m1_dec2024_q3", + "cs404_m1_june2024_q4", + "cs404_m1_june2024_q5", + "cs404_m1_june2024_q6", + "cs404_m1_nov2023_q7", + "cs404_m1_nov2023_q8", + "cs404_m1_nov2023_q9", + "cs404_m1_june2023_q10", + "cs404_m1_june2023_q11", + "cs404_m1_nov2022_q12", + "cs404_m1_nov2022_q13" + ], + "predictedQuestionIds": [] }, { - "id": "module-2", + "id": "cs404-m2", "number": 2, "title": "Control Unit Organization", - "hours": 8, + "hours": null, "topics": [ - "Basic Concept of Instruction", - "Instruction Types", - "Micro Instruction Formats", - "Fetch and Execution cycle", - "Hardwired control unit", - "Microprogrammed Control unit microprogram sequencer Control Memory", - "Sequencing and Execution of Micro Instruction" - ] + { + "id": "cs404-m2-instruction-types", + "slug": "instruction-types", + "title": "Basic Concept of Instruction, Instruction Types", + "displayOrder": 1 + }, + { + "id": "cs404-m2-micro-instruction", + "slug": "micro-instruction-formats", + "title": "Micro Instruction Formats", + "displayOrder": 2 + }, + { + "id": "cs404-m2-fetch-execute", + "slug": "fetch-execution-cycle", + "title": "Fetch and Execution cycle", + "displayOrder": 3 + }, + { + "id": "cs404-m2-hardwired-control", + "slug": "hardwired-control-unit", + "title": "Hardwired control unit", + "displayOrder": 4 + }, + { + "id": "cs404-m2-microprogrammed-control", + "slug": "microprogrammed-control-unit", + "title": "Microprogrammed Control unit microprogram sequencer Control Memory, Sequencing and Execution of Micro Instruction", + "displayOrder": 5 + } + ], + "questionIds": [ + "cs404_m2_june2025_q1", + "cs404_m2_dec2024_q2", + "cs404_m2_dec2024_q3", + "cs404_m2_dec2024_q4", + "cs404_m2_june2024_q5", + "cs404_m2_nov2023_q6", + "cs404_m2_june2023_q7", + "cs404_m2_june2023_q8", + "cs404_m2_nov2022_q9" + ], + "predictedQuestionIds": [] }, { - "id": "module-3", + "id": "cs404-m3", "number": 3, "title": "Computer Arithmetic", - "hours": 8, + "hours": null, "topics": [ - "Addition and Subtraction", - "Tools Compliment Representation", - "Signed Addition and Subtraction", - "Multiplication and division", - "Booths Algorithm", - "Division Operation", - "Floating Point Arithmetic Operation", - "design of Arithmetic unit" - ] + { + "id": "cs404-m3-add-sub", + "slug": "addition-subtraction", + "title": "Addition and Subtraction", + "displayOrder": 1 + }, + { + "id": "cs404-m3-complement", + "slug": "twos-complement-representation", + "title": "Two's Complement Representation, Signed Addition and Subtraction", + "displayOrder": 2 + }, + { + "id": "cs404-m3-multiplication-division", + "slug": "multiplication-division", + "title": "Multiplication and division", + "displayOrder": 3 + }, + { + "id": "cs404-m3-booths-algorithm", + "slug": "booths-algorithm", + "title": "Booth's Algorithm", + "displayOrder": 4 + }, + { + "id": "cs404-m3-division-operation", + "slug": "division-operation", + "title": "Division Operation", + "displayOrder": 5 + }, + { + "id": "cs404-m3-floating-point", + "slug": "floating-point-arithmetic", + "title": "Floating Point Arithmetic Operation", + "displayOrder": 6 + }, + { + "id": "cs404-m3-arithmetic-unit", + "slug": "arithmetic-unit-design", + "title": "Design of Arithmetic unit", + "displayOrder": 7 + } + ], + "questionIds": [ + "cs404_m3_june2025_q1", + "cs404_m3_june2025_q2", + "cs404_m3_june2025_q3", + "cs404_m3_dec2024_q4", + "cs404_m3_dec2024_q5", + "cs404_m3_dec2024_q6", + "cs404_m3_june2024_q7", + "cs404_m3_june2024_q8", + "cs404_m3_june2024_q9", + "cs404_m3_nov2023_q10", + "cs404_m3_june2023_q11", + "cs404_m3_june2023_q12", + "cs404_m3_nov2022_q13", + "cs404_m3_nov2022_q14" + ], + "predictedQuestionIds": [] }, { - "id": "module-4", + "id": "cs404-m4", "number": 4, "title": "I/O Organization", - "hours": 8, + "hours": null, "topics": [ - "I/O Interface –PCI Bus, SCSI Bus, USB", - "Data Transfer: Serial, Parallel, Synchronous, Asynchronous Modes of Data Transfer", - "Direct Memory Access(DMA)", - "I/O Processor" - ] + { + "id": "cs404-m4-io-interface", + "slug": "io-interface-pci-scsi-usb", + "title": "I/O Interface –PCI Bus, SCSI Bus, USB", + "displayOrder": 1 + }, + { + "id": "cs404-m4-data-transfer", + "slug": "data-transfer-modes", + "title": "Data Transfer: Serial, Parallel, Synchronous, Asynchronous Modes of Data Transfer", + "displayOrder": 2 + }, + { + "id": "cs404-m4-dma", + "slug": "direct-memory-access", + "title": "Direct Memory Access(DMA)", + "displayOrder": 3 + }, + { + "id": "cs404-m4-io-processor", + "slug": "io-processor", + "title": "I/O Processor", + "displayOrder": 4 + } + ], + "questionIds": [ + "cs404_m4_june2025_q1", + "cs404_m4_june2025_q2", + "cs404_m4_june2025_q3", + "cs404_m4_june2025_q4", + "cs404_m4_dec2024_q5", + "cs404_m4_dec2024_q6", + "cs404_m4_dec2024_q7", + "cs404_m4_dec2024_q8", + "cs404_m4_june2024_q9", + "cs404_m4_june2024_q10", + "cs404_m4_june2024_q11", + "cs404_m4_june2024_q12", + "cs404_m4_nov2023_q13", + "cs404_m4_nov2023_q14", + "cs404_m4_nov2023_q15", + "cs404_m4_nov2023_q16", + "cs404_m4_june2023_q17", + "cs404_m4_june2023_q18", + "cs404_m4_june2023_q19", + "cs404_m4_nov2022_q20", + "cs404_m4_nov2022_q21" + ], + "predictedQuestionIds": [] }, { - "id": "module-5", + "id": "cs404-m5", "number": 5, "title": "Memory Organization", - "hours": 8, + "hours": null, "topics": [ - "Main memory-RAM, ROM", - "Secondary Memory –Magnetic Tape, Disk, Optical Storage", - "Cache Memory: Cache Structure and Design, Mapping Scheme, Replacement Algorithm, Improving Cache Performance", - "Virtual Memory", - "memory management hardware" - ] + { + "id": "cs404-m5-main-memory", + "slug": "main-memory-ram-rom", + "title": "Main memory-RAM, ROM", + "displayOrder": 1 + }, + { + "id": "cs404-m5-secondary-memory", + "slug": "secondary-memory", + "title": "Secondary Memory –Magnetic Tape, Disk, Optical Storage", + "displayOrder": 2 + }, + { + "id": "cs404-m5-cache-structure", + "slug": "cache-structure-design", + "title": "Cache Memory: Cache Structure and Design", + "displayOrder": 3 + }, + { + "id": "cs404-m5-mapping", + "slug": "cache-mapping-schemes", + "title": "Mapping Scheme", + "displayOrder": 4 + }, + { + "id": "cs404-m5-replacement", + "slug": "replacement-algorithms", + "title": "Replacement Algorithm", + "displayOrder": 5 + }, + { + "id": "cs404-m5-cache-performance", + "slug": "cache-performance-improvement", + "title": "Improving Cache Performance", + "displayOrder": 6 + }, + { + "id": "cs404-m5-virtual-memory", + "slug": "virtual-memory", + "title": "Virtual Memory", + "displayOrder": 7 + }, + { + "id": "cs404-m5-mmu", + "slug": "memory-management-hardware", + "title": "Memory management hardware", + "displayOrder": 8 + } + ], + "questionIds": [ + "cs404_m5_june2025_q1", + "cs404_m5_june2025_q2", + "cs404_m5_june2025_q3", + "cs404_m5_june2025_q4", + "cs404_m5_dec2024_q5", + "cs404_m5_dec2024_q6", + "cs404_m5_dec2024_q7", + "cs404_m5_dec2024_q8", + "cs404_m5_june2024_q9", + "cs404_m5_june2024_q10", + "cs404_m5_june2024_q11", + "cs404_m5_june2024_q12", + "cs404_m5_nov2023_q13", + "cs404_m5_nov2023_q14", + "cs404_m5_nov2023_q15", + "cs404_m5_nov2023_q16", + "cs404_m5_nov2023_q17", + "cs404_m5_june2023_q18", + "cs404_m5_june2023_q19", + "cs404_m5_june2023_q20", + "cs404_m5_nov2022_q21", + "cs404_m5_nov2022_q22", + "cs404_m5_nov2022_q23" + ], + "predictedQuestionIds": [] }, { - "id": "module-6", + "id": "cs404-m6", "number": 6, "title": "Multiprocessors", - "hours": 8, + "hours": null, "topics": [ - "Characteristics of Multiprocessor", - "Structure of Multiprocessor-Inter-processor Arbitration", - "Inter-Processor Communication and Synchronization", - "Memory in Multiprocessor System", - "Concept of Pipelining", - "Vector Processing", - "Array Processing", - "RISC And CISC", - "Study of Multicore Processor –Intel, AMD" - ] + { + "id": "cs404-m6-multiprocessor-structure", + "slug": "multiprocessor-characteristics-structure", + "title": "Characteristics of Multiprocessor, Structure of Multiprocessor", + "displayOrder": 1 + }, + { + "id": "cs404-m6-interprocessor", + "slug": "interprocessor-arbitration-communication", + "title": "Inter-processor Arbitration, Inter-Processor Communication and Synchronization", + "displayOrder": 2 + }, + { + "id": "cs404-m6-memory-mp", + "slug": "memory-multiprocessor-system", + "title": "Memory in Multiprocessor System", + "displayOrder": 3 + }, + { + "id": "cs404-m6-pipelining", + "slug": "pipelining", + "title": "Concept of Pipelining", + "displayOrder": 4 + }, + { + "id": "cs404-m6-vector-array", + "slug": "vector-array-processing", + "title": "Vector Processing, Array Processing", + "displayOrder": 5 + }, + { + "id": "cs404-m6-risc-cisc", + "slug": "risc-and-cisc", + "title": "RISC And CISC", + "displayOrder": 6 + }, + { + "id": "cs404-m6-multicore", + "slug": "multicore-processors", + "title": "Study of Multicore Processor –Intel, AMD", + "displayOrder": 7 + } + ], + "questionIds": [ + "cs404_m6_june2025_q1", + "cs404_m6_june2025_q2", + "cs404_m6_dec2024_q3", + "cs404_m6_dec2024_q4", + "cs404_m6_dec2024_q5", + "cs404_m6_june2024_q6", + "cs404_m6_june2024_q7", + "cs404_m6_june2024_q8", + "cs404_m6_nov2023_q9", + "cs404_m6_nov2023_q10", + "cs404_m6_june2023_q11", + "cs404_m6_june2023_q12", + "cs404_m6_june2023_q13", + "cs404_m6_june2023_q14", + "cs404_m6_nov2022_q15", + "cs404_m6_nov2022_q16", + "cs404_m6_nov2022_q17" + ], + "predictedQuestionIds": [] } ] } diff --git a/content/rgpv/cse/semester-4/cs-405/pyqs.json b/content/rgpv/cse/semester-4/cs-405/pyqs.json index b208aae..19a2086 100644 --- a/content/rgpv/cse/semester-4/cs-405/pyqs.json +++ b/content/rgpv/cse/semester-4/cs-405/pyqs.json @@ -2,8 +2,928 @@ "subject": { "id": "cs-405", "code": "CS-405", - "name": "Operating Systems (OS)", - "title": "CS-405 - Operating Systems (OS)" + "name": "Operating Systems", + "title": "AD/CD/CS/SD-405 (GS) – Operating Systems", + "semester": "IV", + "gradingSystem": "Grading System (GS)", + "maxMarks": 70, + "time": "3 Hours", + "commonInstructions": [ + "Attempt any five questions.", + "All questions carry equal marks." + ] }, - "papers": [] + "papers": [ + { + "exam": "November 2022", + "year": 2022, + "month": "November", + "questions": [ + { + "id": "q1", + "questionNumber": "Q.1", + "subQuestions": [ + { + "id": "q1a", + "label": "a)", + "text": "Explain the different types of services in Operating system and its features.", + "unit": "Unit 1", + "type": "os-basics" + }, + { + "id": "q1b", + "label": "b)", + "text": "Define the Utility programs with example. Explain system call.", + "unit": "Unit 1", + "type": "system-calls" + } + ] + }, + { + "id": "q2", + "questionNumber": "Q.2", + "subQuestions": [ + { + "id": "q2a", + "label": "a)", + "text": "What is Process? Explain the process states diagram.", + "unit": "Unit 3", + "type": "process" + }, + { + "id": "q2b", + "label": "b)", + "text": "Solve using preemptive priority scheduling algorithm for given processes. Draw Gantt chart and calculate Average waiting time and Turnaround time.", + "unit": "Unit 3", + "type": "cpu-scheduling" + } + ] + }, + { + "id": "q3", + "questionNumber": "Q.3", + "subQuestions": [ + { + "id": "q3a", + "label": "a)", + "text": "Consider the given resource allocation graph. Find if the system is in a deadlock state otherwise find a safe sequence.", + "unit": "Unit 4", + "type": "deadlock" + }, + { + "id": "q3b", + "label": "b)", + "text": "Difference between Deadlock and Starvation. Explain the necessary Condition for Deadlock.", + "unit": "Unit 4", + "type": "deadlock" + } + ] + }, + { + "id": "q4", + "questionNumber": "Q.4", + "subQuestions": [ + { + "id": "q4a", + "label": "a)", + "text": "Explain the types of Semaphores in process synchronization.", + "unit": "Unit 4", + "type": "synchronization" + }, + { + "id": "q4b", + "label": "b)", + "text": "What are the different criteria for evaluating the CPU scheduling algorithm?", + "unit": "Unit 3", + "type": "cpu-scheduling" + } + ] + }, + { + "id": "q5", + "questionNumber": "Q.5", + "subQuestions": [ + { + "id": "q5a", + "label": "a)", + "text": "Consider system with byte-addressable memory, 32-bit logical addresses, 4KB page size, 4-byte page table entries. Find page table size in MB.", + "unit": "Unit 3", + "type": "memory" + }, + { + "id": "q5b", + "label": "b)", + "text": "Describe fixed and variable partitioned contiguous memory allocation scheme with merits and demerits.", + "unit": "Unit 3", + "type": "memory" + } + ] + }, + { + "id": "q6", + "questionNumber": "Q.6", + "subQuestions": [ + { + "id": "q6a", + "label": "a)", + "text": "Disk requests for cylinders 10,22,20,2,40,6,38 at cylinder 20. Find total seek time for FCFS and SCAN (6ms/cylinder).", + "unit": "Unit 2", + "type": "disk-scheduling" + }, + { + "id": "q6b", + "label": "b)", + "text": "How many types of disk allocation methods? Describe Indexed method with merits and demerits.", + "unit": "Unit 2", + "type": "file-system" + } + ] + }, + { + "id": "q7", + "questionNumber": "Q.7", + "subQuestions": [ + { + "id": "q7a", + "label": "a)", + "text": "Explain the deadlock recovery in brief.", + "unit": "Unit 4", + "type": "deadlock" + }, + { + "id": "q7b", + "label": "b)", + "text": "Explain the I/O buffering and Interrupt driven operation in short.", + "unit": "Unit 4", + "type": "io" + } + ] + }, + { + "id": "q8", + "questionNumber": "Q.8", + "subQuestions": [ + { + "id": "q8", + "label": "", + "text": "Write short notes on (any two): a) Distributed OS b) Multiprocessor OS c) Network OS d) Paged Segmentation.", + "unit": "Unit 5/3", + "type": "mixed" + } + ] + } + ] + }, + { + "exam": "June 2023", + "year": 2023, + "month": "June", + "questions": [ + { + "id": "q1", + "questionNumber": "Q.1", + "subQuestions": [ + { + "id": "q1a", + "label": "a)", + "text": "Define an operating system. What are the goals of an operating system? Explain.", + "unit": "Unit 1", + "type": "os-basics" + }, + { + "id": "q1b", + "label": "b)", + "text": "Describe the differences among short term, medium term and long term scheduling.", + "unit": "Unit 3", + "type": "cpu-scheduling" + } + ] + }, + { + "id": "q2", + "questionNumber": "Q.2", + "subQuestions": [ + { + "id": "q2a", + "label": "a)", + "text": "What is meant by system call? How it can be used. How does an application program use these call during execution?", + "unit": "Unit 1", + "type": "system-calls" + }, + { + "id": "q2b", + "label": "b)", + "text": "Define Process States. Draw the diagram of PCB.", + "unit": "Unit 3", + "type": "process" + } + ] + }, + { + "id": "q3", + "questionNumber": "Q.3", + "subQuestions": [ + { + "id": "q3a", + "label": "a)", + "text": "Disk drive with 200 cylinders (0-199), work queue: 23,89,132,42,187. Determine total distance for SCAN and LOOK.", + "unit": "Unit 2", + "type": "disk-scheduling" + }, + { + "id": "q3b", + "label": "b)", + "text": "List the advantages and disadvantages of Magnetic Tape memory.", + "unit": "Unit 2", + "type": "file-system" + } + ] + }, + { + "id": "q4", + "questionNumber": "Q.4", + "subQuestions": [ + { + "id": "q4a", + "label": "a)", + "text": "Explain in detail about various ways of free space management.", + "unit": "Unit 2", + "type": "file-system" + }, + { + "id": "q4b", + "label": "b)", + "text": "What is the difference between threads and process.", + "unit": "Unit 3", + "type": "process" + } + ] + }, + { + "id": "q5", + "questionNumber": "Q.5", + "subQuestions": [ + { + "id": "q5a", + "label": "a)", + "text": "Explain paging and segmentation. How are they helpful in removing fragmentation?", + "unit": "Unit 3", + "type": "memory" + }, + { + "id": "q5b", + "label": "b)", + "text": "What is deadlock prevention? A computer has six tape drives, each process needs two. For which values of n is the system deadlock free?", + "unit": "Unit 4", + "type": "deadlock" + } + ] + }, + { + "id": "q6", + "questionNumber": "Q.6", + "subQuestions": [ + { + "id": "q6a", + "label": "a)", + "text": "Explain mutual exclusion with suitable example.", + "unit": "Unit 4", + "type": "synchronization" + }, + { + "id": "q6b", + "label": "b)", + "text": "Discuss Reader-Writers solution using Monitors.", + "unit": "Unit 4", + "type": "synchronization" + } + ] + }, + { + "id": "q7", + "questionNumber": "Q.7", + "subQuestions": [ + { + "id": "q7a", + "label": "a)", + "text": "Explain file system used in Linux and Windows.", + "unit": "Unit 5", + "type": "os-comparison" + }, + { + "id": "q7b", + "label": "b)", + "text": "What is a file? Briefly explain different directory structures. What kind of directory structure is used in UNIX?", + "unit": "Unit 2", + "type": "file-system" + } + ] + }, + { + "id": "q8", + "questionNumber": "Q.8", + "subQuestions": [ + { + "id": "q8", + "label": "", + "text": "Write short notes on: a) Concurrent Programming b) Virus c) Remote Procedure Call (RPC) d) Time Sharing.", + "unit": "Unit 4/5/1", + "type": "mixed" + } + ] + } + ] + }, + { + "exam": "June 2024", + "year": 2024, + "month": "June", + "questions": [ + { + "id": "q1", + "questionNumber": "Q.1", + "subQuestions": [ + { + "id": "q1a", + "label": "a)", + "text": "In multiprogramming/time-sharing, several users share system. What are two security problems? Can same security be ensured as dedicated machine?", + "unit": "Unit 1", + "type": "os-basics" + }, + { + "id": "q1b", + "label": "b)", + "text": "What are the five major activities of an operating system in regards to process management?", + "unit": "Unit 3", + "type": "process" + } + ] + }, + { + "id": "q2", + "questionNumber": "Q.2", + "subQuestions": [ + { + "id": "q2a", + "label": "a)", + "text": "Why do some systems keep track of file type while others don't? Which system is better?", + "unit": "Unit 2", + "type": "file-system" + }, + { + "id": "q2b", + "label": "b)", + "text": "For a file system with 512-byte blocks, explain logical-to-physical address mapping for contiguous, linked and indexed allocation.", + "unit": "Unit 2", + "type": "file-system" + } + ] + }, + { + "id": "q3", + "questionNumber": "Q.3", + "subQuestions": [ + { + "id": "q3a", + "label": "a)", + "text": "What resources are used when a thread is created? How do they differ from process creation?", + "unit": "Unit 3", + "type": "process" + }, + { + "id": "q3b", + "label": "b)", + "text": "Given a segment table, find physical addresses for logical addresses: 0430, 110, 2500, 3400.", + "unit": "Unit 3", + "type": "memory" + } + ] + }, + { + "id": "q4", + "questionNumber": "Q.4", + "subQuestions": [ + { + "id": "q4a", + "label": "a)", + "text": "What is busy waiting? What other kinds of waiting exist? Can busy waiting be avoided?", + "unit": "Unit 4", + "type": "synchronization" + }, + { + "id": "q4b", + "label": "b)", + "text": "Can a system detect starving processes? Explain how or how to deal with starvation.", + "unit": "Unit 3", + "type": "cpu-scheduling" + } + ] + }, + { + "id": "q5", + "questionNumber": "Q.5", + "subQuestions": [ + { + "id": "q5a", + "label": "a)", + "text": "What are the advantages and disadvantages of making the computer network transparent to the user?", + "unit": "Unit 5", + "type": "distributed-os" + }, + { + "id": "q5b", + "label": "b)", + "text": "List three possible types of failures in a distributed system.", + "unit": "Unit 5", + "type": "distributed-os" + } + ] + }, + { + "id": "q6", + "questionNumber": "Q.6", + "subQuestions": [ + { + "id": "q6a", + "label": "a)", + "text": "What are the benefits of mapping objects into virtual memory? Explain.", + "unit": "Unit 3", + "type": "memory" + }, + { + "id": "q6b", + "label": "b)", + "text": "What are the benefits of DFS compared to a file system in a centralized system?", + "unit": "Unit 5", + "type": "distributed-os" + } + ] + }, + { + "id": "q7", + "questionNumber": "Q.7", + "subQuestions": [ + { + "id": "q7a", + "label": "a)", + "text": "Why Semaphore is important in OS? Explain Binary and counting semaphores with example.", + "unit": "Unit 4", + "type": "synchronization" + }, + { + "id": "q7b", + "label": "b)", + "text": "What is Overlay? How do dynamic linking and loading perform in memory management?", + "unit": "Unit 3", + "type": "memory" + } + ] + }, + { + "id": "q8", + "questionNumber": "Q.8", + "subQuestions": [ + { + "id": "q8", + "label": "", + "text": "Write short notes on (any two): a) Synchronization b) Paging c) System Calls.", + "unit": "Unit 4/3/1", + "type": "mixed" + } + ] + } + ] + }, + { + "exam": "December 2024", + "year": 2024, + "month": "December", + "questions": [ + { + "id": "q1", + "questionNumber": "Q.1", + "subQuestions": [ + { + "id": "q1", + "label": "", + "text": "Explain the need for the Process Control Block (PCB) fields.", + "unit": "Unit 3", + "type": "process" + } + ] + }, + { + "id": "q2", + "questionNumber": "Q.2", + "subQuestions": [ + { + "id": "q2", + "label": "", + "text": "Given processes with burst time, priority and arrival time. Find scheduling sequence, turnaround time and waiting time for FCFS, RR(q=3), preemptive SJF.", + "unit": "Unit 3", + "type": "cpu-scheduling" + } + ] + }, + { + "id": "q3", + "questionNumber": "Q.3", + "subQuestions": [ + { + "id": "q3", + "label": "", + "text": "How multilevel feedback queue scheduling differs from multilevel queue scheduling.", + "unit": "Unit 3", + "type": "cpu-scheduling" + } + ] + }, + { + "id": "q4", + "questionNumber": "Q.4", + "subQuestions": [ + { + "id": "q4", + "label": "", + "text": "What is Resource Allocation Graph? Explain occurrence and avoidance of deadlock among 3 processes and 3 resources.", + "unit": "Unit 4", + "type": "deadlock" + } + ] + }, + { + "id": "q5", + "questionNumber": "Q.5", + "subQuestions": [ + { + "id": "q5", + "label": "", + "text": "Page requests: 1,2,3,5,4,1,2,5,3,2,4,3. With three frames, how many page faults using Optimal Page Replacement?", + "unit": "Unit 3", + "type": "memory" + } + ] + }, + { + "id": "q6", + "questionNumber": "Q.6", + "subQuestions": [ + { + "id": "q6", + "label": "", + "text": "Write short notes on (any two): a) Thrashing b) LRU algorithm c) PCB d) Contiguous and Linked Disk Allocation e) Optimal Page Replacement f) Interrupts g) Multilevel Feedback Queue Scheduling.", + "unit": "Unit 3/2/4", + "type": "mixed" + } + ] + }, + { + "id": "q7", + "questionNumber": "Q.7", + "subQuestions": [ + { + "id": "q7", + "label": "", + "text": "Define the term 'Directory'. Explain any two schemes of logical directory structures.", + "unit": "Unit 2", + "type": "file-system" + } + ] + }, + { + "id": "q8", + "questionNumber": "Q.8", + "subQuestions": [ + { + "id": "q8", + "label": "", + "text": "When do page-faults occur? Describe the action taken by the OS when page-fault occurs.", + "unit": "Unit 3", + "type": "memory" + } + ] + } + ] + }, + { + "exam": "June 2025", + "year": 2025, + "month": "June", + "questions": [ + { + "id": "q1", + "questionNumber": "Q.1", + "subQuestions": [ + { + "id": "q1a", + "label": "a)", + "text": "What are the five major activities of an operating system in regards to memory management?", + "unit": "Unit 3", + "type": "memory" + }, + { + "id": "q1b", + "label": "b)", + "text": "List the functions of OS. How operating system perform management task in a system?", + "unit": "Unit 1", + "type": "os-basics" + } + ] + }, + { + "id": "q2", + "questionNumber": "Q.2", + "subQuestions": [ + { + "id": "q2a", + "label": "a)", + "text": "Give an example of an application where data should be accessed sequentially and randomly.", + "unit": "Unit 2", + "type": "file-system" + }, + { + "id": "q2b", + "label": "b)", + "text": "Disk with 5000 cylinders at cylinder 143, previous at 125. Find total distance for SSTF, SCAN and LOOK for given queue.", + "unit": "Unit 2", + "type": "disk-scheduling" + } + ] + }, + { + "id": "q3", + "questionNumber": "Q.3", + "subQuestions": [ + { + "id": "q3a", + "label": "a)", + "text": "Consider variant of RR where entries in ready queue are pointers to PCB. Effect of two pointers to same process? Major advantage and drawback?", + "unit": "Unit 3", + "type": "cpu-scheduling" + }, + { + "id": "q3b", + "label": "b)", + "text": "How many page faults for optimal page replacement with 4 frames for given reference string?", + "unit": "Unit 3", + "type": "memory" + } + ] + }, + { + "id": "q4", + "questionNumber": "Q.4", + "subQuestions": [ + { + "id": "q4a", + "label": "a)", + "text": "Process P wants to wait for two messages from mailbox A and B. What sequence of send/receive?", + "unit": "Unit 4", + "type": "ipc" + }, + { + "id": "q4b", + "label": "b)", + "text": "Why use interrupt-driven I/O for single serial port but polling I/O for terminal concentrator?", + "unit": "Unit 4", + "type": "io" + } + ] + }, + { + "id": "q5", + "questionNumber": "Q.5", + "subQuestions": [ + { + "id": "q5a", + "label": "a)", + "text": "What aspects of a distributed system would you select for a system running on a totally reliable network?", + "unit": "Unit 5", + "type": "distributed-os" + }, + { + "id": "q5b", + "label": "b)", + "text": "List three possible types of failures in a distributed system.", + "unit": "Unit 5", + "type": "distributed-os" + } + ] + }, + { + "id": "q6", + "questionNumber": "Q.6", + "subQuestions": [ + { + "id": "q6a", + "label": "a)", + "text": "Define a semaphore for dining philosopher's problem.", + "unit": "Unit 4", + "type": "synchronization" + }, + { + "id": "q6b", + "label": "b)", + "text": "Describe method for process migration across different architectures running same OS and different OS.", + "unit": "Unit 5", + "type": "distributed-os" + } + ] + }, + { + "id": "q7", + "questionNumber": "Q.7", + "subQuestions": [ + { + "id": "q7a", + "label": "a)", + "text": "Explain concurrency controls. Differences between real and virtual concurrency?", + "unit": "Unit 4", + "type": "synchronization" + }, + { + "id": "q7b", + "label": "b)", + "text": "How process is differing from program? Describe process transition diagram in detail.", + "unit": "Unit 3", + "type": "process" + } + ] + }, + { + "id": "q8", + "questionNumber": "Q.8", + "subQuestions": [ + { + "id": "q8", + "label": "", + "text": "Write short notes on (any two): a) Deadlock prevention and avoidance b) Kernel architecture in Unix c) System calls.", + "unit": "Unit 4/5/1", + "type": "mixed" + } + ] + } + ] + }, + { + "exam": "December 2025", + "year": 2025, + "month": "December", + "questions": [ + { + "id": "q1", + "questionNumber": "Q.1", + "subQuestions": [ + { + "id": "q1a", + "label": "a)", + "text": "Explain the evolution of operating system in detail.", + "unit": "Unit 1", + "type": "os-basics" + }, + { + "id": "q1b", + "label": "b)", + "text": "List the functions of OS. How operating system perform management task in a system?", + "unit": "Unit 1", + "type": "os-basics" + } + ] + }, + { + "id": "q2", + "questionNumber": "Q.2", + "subQuestions": [ + { + "id": "q2a", + "label": "a)", + "text": "What is a File? Write different file attributes and operations?", + "unit": "Unit 2", + "type": "file-system" + }, + { + "id": "q2b", + "label": "b)", + "text": "For a file system with 512-byte blocks, explain logical-to-physical address mapping for contiguous, linked and indexed allocation.", + "unit": "Unit 2", + "type": "file-system" + } + ] + }, + { + "id": "q3", + "questionNumber": "Q.3", + "subQuestions": [ + { + "id": "q3a", + "label": "a)", + "text": "How process is differing from program? Describe process transition diagram in detail.", + "unit": "Unit 3", + "type": "process" + }, + { + "id": "q3b", + "label": "b)", + "text": "Given a segment table, find physical addresses for logical addresses: 0430, 110, 2500, 3400.", + "unit": "Unit 3", + "type": "memory" + } + ] + }, + { + "id": "q4", + "questionNumber": "Q.4", + "subQuestions": [ + { + "id": "q4a", + "label": "a)", + "text": "What are the five major activities of an operating system in regards to memory management?", + "unit": "Unit 3", + "type": "memory" + }, + { + "id": "q4b", + "label": "b)", + "text": "What is busy waiting? What other kinds of waiting exist? Can busy waiting be avoided?", + "unit": "Unit 4", + "type": "synchronization" + } + ] + }, + { + "id": "q5", + "questionNumber": "Q.5", + "subQuestions": [ + { + "id": "q5a", + "label": "a)", + "text": "Explain concurrency controls. Differences between real and virtual concurrency?", + "unit": "Unit 4", + "type": "synchronization" + }, + { + "id": "q5b", + "label": "b)", + "text": "Explain the concept of buffering and spooling.", + "unit": "Unit 4", + "type": "io" + } + ] + }, + { + "id": "q6", + "questionNumber": "Q.6", + "subQuestions": [ + { + "id": "q6a", + "label": "a)", + "text": "Why Semaphore is important in OS? Explain Binary and counting semaphores with suitable example.", + "unit": "Unit 4", + "type": "synchronization" + }, + { + "id": "q6b", + "label": "b)", + "text": "What are the advantages and disadvantages of making the computer network transparent to the user?", + "unit": "Unit 5", + "type": "distributed-os" + } + ] + }, + { + "id": "q7", + "questionNumber": "Q.7", + "subQuestions": [ + { + "id": "q7a", + "label": "a)", + "text": "Discuss the design issues of distributed operating system.", + "unit": "Unit 5", + "type": "distributed-os" + }, + { + "id": "q7b", + "label": "b)", + "text": "List three possible types of failures in a distributed system.", + "unit": "Unit 5", + "type": "distributed-os" + } + ] + }, + { + "id": "q8", + "questionNumber": "Q.8", + "subQuestions": [ + { + "id": "q8", + "label": "", + "text": "Write short notes on (any two): a) Synchronization b) Demand paging c) System calls d) Kernel architecture in Unix.", + "unit": "Unit 4/3/1/5", + "type": "mixed" + } + ] + } + ] + } + ] } diff --git a/content/rgpv/cse/semester-4/cs-405/syllabus.json b/content/rgpv/cse/semester-4/cs-405/syllabus.json index c2dcaf2..6aacfe0 100644 --- a/content/rgpv/cse/semester-4/cs-405/syllabus.json +++ b/content/rgpv/cse/semester-4/cs-405/syllabus.json @@ -3,86 +3,251 @@ "id": "cs-405", "code": "CS-405", "name": "Operating Systems", - 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