ADC takes impl Into<DynPclk>

Author: jbeaurivage

boards/examples/m4-adc.rs

@@ -44,7 +44,7 @@ fn main() -> ! {
     let apb_adc0 = buses.apb.enable(tokens.apbs.adc0);
     // ...and enable the ADC0 PCLK. Both of these are required for the
     // ADC to run.
-    let (pclk_adc0, _gclk0) = Pclk::enable_dyn(tokens.pclks.adc0, clocks.gclk0);
+    let (pclk_adc0, _gclk0) = Pclk::enable(tokens.pclks.adc0, clocks.gclk0);
 
     let mut adc = AdcBuilder::new(Accumulation::single(atsamd_hal::adc::AdcResolution::_12))
         .with_clock_cycles_per_sample(5)

hal/src/peripherals/adc/builder.rs

@@ -244,17 +244,19 @@ impl AdcBuilder {
         Ok(adc_clk_freq / clocks_per_sample)
     }
 
-    /// Turn the builder into an ADC
+    /// Turn the builder into an ADC.
+    ///
+    /// This function will convert the provided [`Pclk`](crate::clock::v2::pclk::Pclk) into a [`DynPclk`].
     #[hal_cfg("adc-d5x")]
     #[inline]
     pub fn enable<I: AdcInstance>(
         self,
         adc: I::Instance,
         clk: crate::clock::v2::apb::ApbClk<I::ClockId>,
-        pclk: crate::clock::v2::pclk::Pclk<I::ClockId, crate::clock::v2::pclk::DynPclkSourceId>,
+        pclk: impl Into<crate::clock::v2::pclk::DynPclk<I::ClockId>>,
     ) -> Result<Adc<I>, BuilderError> {
         let settings = self.to_settings()?;
-        Adc::new(adc, settings, clk, pclk).map_err(|e| e.into())
+        Adc::new(adc, settings, clk, pclk.into()).map_err(|e| e.into())
     }
 
     #[hal_cfg(any("adc-d11", "adc-d21"))]

hal/src/peripherals/adc/mod.rs

@@ -49,10 +49,7 @@ pub use builder::*;
 use crate::pac::adc as adc0;
 #[hal_cfg("adc-d5x")]
 use crate::{
-    clock::v2::{
-        apb::ApbClk,
-        pclk::{DynPclkSourceId, Pclk},
-    },
+    clock::v2::{apb::ApbClk, pclk::DynPclk},
     pac::adc0,
 };
 
@@ -181,7 +178,7 @@ pub struct Adc<I: AdcInstance> {
 pub struct Adc<I: AdcInstance> {
     adc: I::Instance,
     _apbclk: ApbClk<I::ClockId>,
-    _pclk: Pclk<I::ClockId, DynPclkSourceId>,
+    _pclk: DynPclk<I::ClockId>,
     cfg: AdcSettings,
     discard: bool,
 }
@@ -214,7 +211,7 @@ impl<I: AdcInstance> Adc<I> {
         adc: I::Instance,
         settings: AdcSettings,
         clk: ApbClk<I::ClockId>,
-        pclk: Pclk<I::ClockId, DynPclkSourceId>,
+        pclk: DynPclk<I::ClockId>,
     ) -> Result<Self, Error> {
         // TODO: Ideally, the ADC struct would take ownership of the Pclk type here.
         // However, since clock::v2 is not implemented for all chips yet, the
@@ -430,15 +427,8 @@ impl<I: AdcInstance> Adc<I> {
 
     /// Return the underlying ADC PAC object and the enabled APB ADC clock.
     #[hal_cfg("adc-d5x")]
-    #[allow(clippy::type_complexity)]
     #[inline]
-    pub fn free(
-        mut self,
-    ) -> (
-        I::Instance,
-        ApbClk<I::ClockId>,
-        Pclk<I::ClockId, DynPclkSourceId>,
-    ) {
+    pub fn free(mut self) -> (I::Instance, ApbClk<I::ClockId>, DynPclk<I::ClockId>) {
         self.software_reset();
         (self.adc, self._apbclk, self._pclk)
     }