Add port-aliasing support for Mosaic integration (P/N → p1/p2)

[cdaunt]

Problem

When Mosaic schematics use built-in electronic components (resistor, capacitor, inductor), the kfnetlist emits:

• Component names: lowercase (resistor, capacitor, inductor)
• Port names: P and N

Circulax's electronic.py defines these as:

• Component names: PascalCase (Resistor, Capacitor, Inductor)
• Port names: p1 and p2

The circulax compiler in compiler.py iterates comp_cls.ports and looks up f"{inst_name},{port}" in the port-to-node map. When the netlist uses P/N but the component declares p1/p2, the lookup fails with an "unconnected port" error.

Current workaround

GDSFactory+ currently defines standalone R/L/C components in simulate_circulax.py with Mosaic-compatible port names (P, N) and property names (resistance, capacitance, inductance). This duplicates the physics from circulax.components.electronic.

Proposed solution

Add a mechanism to create port-aliased variants of existing components, or support a port-name mapping at compile time. Something like:

# Option A: Port alias on the component class
@component(ports=("P", "N"), port_aliases={"P": "p1", "N": "p2"})

# Option B: Compile-time port remapping
compile_circuit(netlist, models, port_map={"resistor": {"P": "p1", "N": "p2"}})

# Option C: Case-insensitive + positional fallback in the compiler
# If exact port name not found, try positional matching against comp_cls.ports

This would let integrators reuse circulax's canonical components without re-implementing the physics.