Skip to content

Commit 94cfd60

Browse files
committed
Add GARATRONIC_PYMATE_CORE
1 parent b67ac73 commit 94cfd60

8 files changed

Lines changed: 351 additions & 1 deletion

File tree

Lines changed: 45 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,45 @@
1+
/*
2+
* This file is part of the MicroPython project, http://micropython.org/
3+
*
4+
* The MIT License (MIT)
5+
*
6+
* Copyright (c) 2025 Garatronic, thanks to Damien P. George
7+
*
8+
* Permission is hereby granted, free of charge, to any person obtaining a copy
9+
* of this software and associated documentation files (the "Software"), to deal
10+
* in the Software without restriction, including without limitation the rights
11+
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12+
* copies of the Software, and to permit persons to whom the Software is
13+
* furnished to do so, subject to the following conditions:
14+
*
15+
* The above copyright notice and this permission notice shall be included in
16+
* all copies or substantial portions of the Software.
17+
*
18+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21+
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22+
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23+
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24+
* THE SOFTWARE.
25+
*/
26+
27+
#include "storage.h"
28+
#include "qspi.h"
29+
30+
#if MICROPY_HW_SPIFLASH_ENABLE_CACHE
31+
// Shared cache for first SPI block device
32+
static mp_spiflash_cache_t spi_bdev_cache;
33+
#endif
34+
35+
// First external SPI flash uses hardware QSPI interface
36+
const mp_spiflash_config_t spiflash_config = {
37+
.bus_kind = MP_SPIFLASH_BUS_QSPI,
38+
.bus.u_qspi.data = NULL,
39+
.bus.u_qspi.proto = &qspi_proto,
40+
#if MICROPY_HW_SPIFLASH_ENABLE_CACHE
41+
.cache = &spi_bdev_cache,
42+
#endif
43+
};
44+
45+
spi_bdev_t spi_bdev;
Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,15 @@
1+
{
2+
"deploy": [
3+
"../deploy.md"
4+
],
5+
"docs": "",
6+
"features": [],
7+
"images": [
8+
"PyMateIO_Core.jpg"
9+
],
10+
"mcu": "stm32f4",
11+
"product": "GARATRONIC_PYMATE_CORE",
12+
"thumbnail": "",
13+
"url": "https://www.pymate.io/product/pymateio-core-8-digital-analog-inputs-8-digital-outputs-rs485-port-can-port/",
14+
"vendor": "PyMateIO"
15+
}
Lines changed: 45 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,45 @@
1+
/*
2+
Linker script for PYBSTICK26-PRO with STM32F412 + QSPI flash
3+
4+
Memory layout for mboot configuration (this here describes the app part):
5+
6+
FLASH_APP .isr_vector
7+
FLASH_APP .text
8+
FLASH_APP .data
9+
10+
RAM .data
11+
RAM .bss
12+
RAM .heap
13+
RAM .stack
14+
*/
15+
16+
/* Specify the memory areas */
17+
MEMORY
18+
{
19+
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K /* sectors 0-1 */
20+
FLASH_APP (rx) : ORIGIN = 0x08000000, LENGTH = 512K /* sectors 2-7 */
21+
FLASH_QSPI (rx) : ORIGIN = 0x90000000, LENGTH = 1024K /* external QSPI */
22+
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K /* SRAM */
23+
}
24+
25+
/* produce a link error if there is not this amount of RAM for these sections */
26+
_minimum_stack_size = 2K;
27+
_minimum_heap_size = 16K;
28+
29+
/* Define the stack. The stack is full descending so begins just above last byte
30+
of RAM. Note that EABI requires the stack to be 8-byte aligned for a call. */
31+
_estack = ORIGIN(RAM) + LENGTH(RAM) - _estack_reserve;
32+
_sstack = _estack - 16K;
33+
34+
/* RAM extents for the garbage collector */
35+
_ram_start = ORIGIN(RAM);
36+
_ram_end = ORIGIN(RAM) + LENGTH(RAM);
37+
_heap_start = _ebss; /* heap starts just after statically allocated memory */
38+
_heap_end = _sstack;
39+
40+
/* ROMFS location */
41+
_micropy_hw_romfs_part0_start = ORIGIN(FLASH_QSPI);
42+
_micropy_hw_romfs_part0_size = LENGTH(FLASH_QSPI);
43+
44+
_micropy_hw_internal_flash_storage_start = ORIGIN (FLASH_QSPI);
45+
_micropy_hw_internal_flash_storage_end = ORIGIN(FLASH_QSPI) + LENGTH(FLASH_QSPI);
Lines changed: 157 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,157 @@
1+
/*
2+
* This file is part of the MicroPython project, http://micropython.org/
3+
*
4+
* The MIT License (MIT)
5+
*
6+
* Copyright (c) 2025 Garatronic SAS, thanks to Damien P. George
7+
*
8+
* Permission is hereby granted, free of charge, to any person obtaining a copy
9+
* of this software and associated documentation files (the "Software"), to deal
10+
* in the Software without restriction, including without limitation the rights
11+
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12+
* copies of the Software, and to permit persons to whom the Software is
13+
* furnished to do so, subject to the following conditions:
14+
*
15+
* The above copyright notice and this permission notice shall be included in
16+
* all copies or substantial portions of the Software.
17+
*
18+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21+
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22+
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23+
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24+
* THE SOFTWARE.
25+
*/
26+
27+
#define MICROPY_HW_BOARD_NAME "PymateIO CORE8ADI8DOSC V0.2.0"
28+
#define MICROPY_HW_MCU_NAME "STM32F412RE"
29+
#define MICROPY_PY_THREAD (1)
30+
31+
#define MICROPY_PY_PYB_LEGACY (1)
32+
#define MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE (0)
33+
#define MICROPY_HW_HAS_SWITCH (1)
34+
#define MICROPY_HW_HAS_FLASH (1)
35+
#define MICROPY_HW_ENABLE_RNG (1)
36+
#define MICROPY_HW_ENABLE_RTC (1)
37+
#define MICROPY_HW_ENABLE_USB (1)
38+
#define MICROPY_HW_ENABLE_SERVO (1)
39+
#define MICROPY_HW_ENABLE_DAC (0)
40+
#define MICROPY_HW_ENABLE_SDCARD (0)
41+
#define MICROPY_HW_ENABLE_MMCARD (0)
42+
43+
// board HSE is 16MHz, run SYS at 96 MHz
44+
// board is 3.3V powered, 75 to 100 MHz: 3 wait states
45+
#define MICROPY_HW_CLK_PLLM (16)
46+
#define MICROPY_HW_CLK_PLLN (192)
47+
#define MICROPY_HW_CLK_PLLP (RCC_PLLP_DIV2)
48+
#define MICROPY_HW_CLK_PLLQ (4)
49+
#define MICROPY_HW_CLK_LAST_FREQ (1)
50+
#define MICROPY_HW_CLK_AHB_DIV (RCC_SYSCLK_DIV1)
51+
#define MICROPY_HW_CLK_APB1_DIV (RCC_HCLK_DIV2)
52+
#define MICROPY_HW_CLK_APB2_DIV (RCC_HCLK_DIV1)
53+
#define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_3
54+
55+
// board haves 32kHz crystal
56+
#define MICROPY_HW_RTC_USE_LSE (1)
57+
#define MICROPY_HW_RTC_USE_US (1)
58+
#define MICROPY_HW_RTC_USE_CALOUT (0)
59+
60+
61+
// 8MBit external QSPI flash
62+
#define MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2 (23)
63+
#define MICROPY_HW_QSPIFLASH_CS (pin_B6)
64+
#define MICROPY_HW_QSPIFLASH_SCK (pin_B2)
65+
#define MICROPY_HW_QSPIFLASH_IO0 (pin_C9)
66+
#define MICROPY_HW_QSPIFLASH_IO1 (pin_C10)
67+
#define MICROPY_HW_QSPIFLASH_IO2 (pin_C8)
68+
#define MICROPY_HW_QSPIFLASH_IO3 (pin_A1)
69+
70+
// ROMFS config
71+
#define MICROPY_HW_ROMFS_ENABLE_EXTERNAL_QSPI (1)
72+
#define MICROPY_HW_ROMFS_QSPI_SPIFLASH_OBJ (&spi_bdev.spiflash)
73+
#define MICROPY_HW_ROMFS_ENABLE_PART0 (1)
74+
75+
// SPI flash, block device config (when used as the filesystem)
76+
extern const struct _mp_spiflash_config_t spiflash_config;
77+
extern struct _spi_bdev_t spi_bdev;
78+
79+
#if !USE_QSPI_XIP
80+
#define MICROPY_HW_SPIFLASH_ENABLE_CACHE (1)
81+
#define MICROPY_HW_BDEV_SPIFLASH (&spi_bdev)
82+
#define MICROPY_HW_BDEV_SPIFLASH_CONFIG (&spiflash_config)
83+
#define MICROPY_HW_BDEV_SPIFLASH_SIZE_BYTES ((1 << MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2) / 8)
84+
#define MICROPY_HW_BDEV_SPIFLASH_EXTENDED (&spi_bdev) // for extended block protocol
85+
#endif
86+
87+
// UART config
88+
#define MICROPY_HW_UART1_NAME "X"
89+
#define MICROPY_HW_UART1_TX (pin_A15)
90+
#define MICROPY_HW_UART1_RX (pin_A10)
91+
#define MICROPY_HW_UART2_NAME "M"
92+
#define MICROPY_HW_UART2_TX (pin_A2)
93+
#define MICROPY_HW_UART2_RX (pin_A3)
94+
95+
96+
// I2C buses
97+
// putain de fmpi2c controleur, ne marche pas encore :-(
98+
//#define MICROPY_HW_I2C4_NAME "X"
99+
//#define MICROPY_HW_I2C4_SCL (pin_B15)
100+
//#define MICROPY_HW_I2C4_SDA (pin_B14)
101+
//#define MICROPY_HW_I2C4_SMB (pin_B13)
102+
103+
// CAN buse
104+
#define MICROPY_HW_CAN1_NAME "X"
105+
#define MICROPY_HW_CAN1_TX (pin_B9)
106+
#define MICROPY_HW_CAN1_RX (pin_B8)
107+
108+
// SPI buses
109+
#define MICROPY_HW_SPI1_NAME "X"
110+
#define MICROPY_HW_SPI1_NSS (pin_A4)
111+
#define MICROPY_HW_SPI1_SCK (pin_B3)
112+
#define MICROPY_HW_SPI1_MISO (pin_B4)
113+
#define MICROPY_HW_SPI1_MOSI (pin_B5)
114+
115+
// USRSW has external pullup, and pressing the switch makes the input go low
116+
#define MICROPY_HW_USRSW_PIN (pin_B12)
117+
#define MICROPY_HW_USRSW_PULL (GPIO_PULLUP)
118+
#define MICROPY_HW_USRSW_EXTI_MODE (GPIO_MODE_IT_FALLING)
119+
#define MICROPY_HW_USRSW_PRESSED (0)
120+
121+
// The board has 2 LEDs, LED1 & LED2 as fusionned
122+
#define MICROPY_HW_LED1 (pin_A13) // RED legacy
123+
#define MICROPY_HW_LED2 (pin_A13) // GREEN legacy
124+
#define MICROPY_HW_LED3 (pin_A14) // YELLOW lecacy
125+
#define MICROPY_HW_LED_ON(pin) (mp_hal_pin_high(pin))
126+
#define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_low(pin))
127+
128+
// USB config
129+
#define MICROPY_HW_USB_FS (1)
130+
#define MICROPY_HW_FLASH_FS_LABEL "pymate_io"
131+
132+
/******************************************************************************/
133+
// Mboot bootloader configuration : only for QSPI version
134+
// else STM32 rom based bootloader with BOOT0 trigger at reset need to be used
135+
136+
//#define MBOOT_SPIFLASH_ADDR (0x90000000)
137+
//#define MBOOT_SPIFLASH_BYTE_SIZE (1024 * 1024)
138+
//#define MBOOT_SPIFLASH_LAYOUT "/0x90000000/256*4Kg"
139+
//#define MBOOT_SPIFLASH_ERASE_BLOCKS_PER_PAGE (1)
140+
//#define MBOOT_SPIFLASH_SPIFLASH (&spi_bdev.spiflash)
141+
//#define MBOOT_SPIFLASH_CONFIG (&spiflash_config)
142+
143+
//#define MBOOT_USB_AUTODETECT_PORT (1)
144+
//#define MBOOT_FSLOAD (1)
145+
//#define MBOOT_VFS_LFS2 (1)
146+
147+
//#define MBOOT_BOOTPIN_PIN (pin_B12)
148+
//#define MBOOT_BOOTPIN_PULL (MP_HAL_PIN_PULL_UP)
149+
//#define MBOOT_BOOTPIN_ACTIVE (0)
150+
151+
// #define MBOOT_I2C_PERIPH_ID 1
152+
// #define MBOOT_I2C_SCL (pin_B8)
153+
// #define MBOOT_I2C_SDA (pin_B9)
154+
// #define MBOOT_I2C_ALTFUNC (4)
155+
156+
//#define MBOOT_BOARD_EARLY_INIT(initial_r0) mboot_board_early_init()
157+
//void mboot_board_early_init(void);
Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,19 @@
1+
# MCU settings
2+
MCU_SERIES = f4
3+
CMSIS_MCU = STM32F412Rx
4+
MICROPY_FLOAT_IMPL = single
5+
AF_FILE = boards/stm32f412_af.csv
6+
LD_FILES = boards/GARATRONIC_PYMATE_CORE/f412_qspi.ld boards/common_bl.ld
7+
TEXT0_ADDR = 0x08000000
8+
TEXT0_SECTIONS = .isr_vector .text .data .ARM
9+
10+
# MicroPython settings
11+
MICROPY_VFS_LFS2 = 1
12+
13+
#I2C4 needs fmpi2c
14+
SRC_HAL += $(STM32LIB_HAL_BASE)/Src/stm32f4xx_hal_fmpi2c.c
15+
16+
# wiznet5k module for ethernet support; valid values are:
17+
# 0 : no Wiznet support
18+
# 5500 : support for W5500 module
19+
MICROPY_PY_NETWORK_WIZNET5K = 5500
Lines changed: 45 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,45 @@
1+
In1,PA0
2+
In2,PC4
3+
In3,PB0
4+
In4,PB1
5+
In5,PC0
6+
In6,PC1
7+
In7,PC2
8+
In8,PC3
9+
Out1,PA7
10+
Out2,PA6
11+
Out3,PC6
12+
Out4,PC7
13+
Out5,PA8
14+
Out6,PA9
15+
Out7,PB7
16+
Out8,PD2
17+
MES_VIN,PA5
18+
USER_SW,PB12
19+
LED_1,PA13
20+
LED_2,PA14
21+
USB_DM,PA11
22+
USB_DP,PA12
23+
UART1_TX,PA15
24+
UART1_RX,PA10
25+
RS422_TX,PA2
26+
RS422_RX,PA3
27+
RS422_MODE,PC12
28+
CAN1_RX,PB8
29+
CAN1_TX,PB9
30+
CAN1_SB,PC11
31+
I2C4_SMB,PB13
32+
I2C4_SDA,PB14
33+
I2C4_SCL,PB15
34+
UART3_TX,PB10
35+
UART3_RX,PC5
36+
SPI1_MOSI,PB5
37+
SPI1_MISO,PB4
38+
SPI1_SCLK,PB3
39+
SPI1_NSS,PA4
40+
QSPI1_D0,PC9
41+
QSPI1_D1,PC10
42+
QSPI1_D2,PC8
43+
QSPI1_D3,PA1
44+
QSPI1_CS,PB6
45+
QSPI1_CLK,PB2
Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,22 @@
1+
/* This file is part of the MicroPython project, http://micropython.org/
2+
* The MIT License (MIT)
3+
* Copyright (c) 2019 Damien P. George
4+
*/
5+
#ifndef MICROPY_INCLUDED_STM32F4XX_HAL_CONF_H
6+
#define MICROPY_INCLUDED_STM32F4XX_HAL_CONF_H
7+
8+
#define HAL_FMPI2C_MODULE_ENABLED
9+
10+
// Oscillator values in Hz
11+
#define HSE_VALUE (16000000)
12+
#define LSE_VALUE (32768)
13+
#define EXTERNAL_CLOCK_VALUE (12288000)
14+
15+
// Oscillator timeouts in ms
16+
#define HSE_STARTUP_TIMEOUT (100)
17+
#define LSE_STARTUP_TIMEOUT (5000)
18+
19+
#include "boards/stm32f4xx_hal_conf_base.h"
20+
#include "stm32f4xx_hal_fmpi2c.h"
21+
22+
#endif // MICROPY_INCLUDED_STM32F4XX_HAL_CONF_H

ports/stm32/mpu.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,9 @@
2828

2929
#include "irq.h"
3030

31-
#if (defined(STM32F4) && defined(MICROPY_HW_ETH_MDC)) || defined(STM32F469xx) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB)
31+
#if (defined(STM32F4) && defined(MICROPY_HW_ETH_MDC)) || \
32+
defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || \
33+
defined(STM32F469xx) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB)
3234

3335
#define MPU_REGION_ETH (MPU_REGION_NUMBER0)
3436
#define MPU_REGION_QSPI1 (MPU_REGION_NUMBER1)

0 commit comments

Comments
 (0)